[M] Change in coreboot[master]: checkpoint commit

[ron minnich (Code Review)]

Attention is currently required from: Philipp Hug.

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81131?usp=email )

Change subject: checkpoint commit
......................................................................

checkpoint commit

Change-Id: I013663c7b68abf7b3b8a9dd89d9a585445fee3f1
Signed-off-by: Ronald G Minnich 
---
M src/arch/riscv/boot.c
M src/arch/riscv/payload.c
M src/arch/riscv/pmp.c
M src/arch/riscv/virtual_memory.c
4 files changed, 42 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/81131/1

diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index ea22774..ebdee88 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <delay.h>
 #include <program_loading.h>
 #include <vm.h>
 #include <arch/boot.h>
@@ -50,6 +51,11 @@
 void arch_prog_run(struct prog *prog)
 {
    struct arch_prog_run_args args = {};
+	int hart_id = HLS()->hart_id;
+
+	for (;hart_id != CONFIG_RISCV_WORKING_HARTID;) {
+		mdelay(1000);
+	}

args.prog = prog;

@@ -63,5 +69,6 @@
    	args.opensbi = &sbi;
    }

+	printk(BIOS_EMERG, "resuming hart %d\n", hart_id);
    smp_resume((void (*)(void *))do_arch_prog_run, &args);
 }
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 3c92c0b..a7a7dcb 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <delay.h>
 #include <program_loading.h>
 #include <stdint.h>
 #include <arch/boot.h>
@@ -62,13 +63,17 @@
    uintptr_t status = read_csr(mstatus);
    status = INSERT_FIELD(status, MSTATUS_MPIE, 0);

+	mdelay(1000 * hart_id);
+	printk(BIOS_EMERG, "%s: hart %d\n", __func__, hart_id);
    switch (payload_mode) {
    case RISCV_PAYLOAD_MODE_S:
    	mstatus_init();
-		//reset_pmp();
+		reset_pmp();
    	//	setup_pmp(0x84000000, 0xc0000000-0x84000000, PMP_R | PMP_W | PMP_X);
-		setup_pmp(0, (u64)256 * 1024 * 1024 * 1024, PMP_R | PMP_W | PMP_X);
-		//status = 0;
+		setup_pmp(0x20000000, 1<<10,  0);
+		setup_pmp(0x80000000, 1<<12, 0);
+		setup_pmp(0, 0xffffffffffffffff+1, PMP_R | PMP_W | PMP_X);
+		status = 0;
    	status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);

/* Trap vector base address point to the payload */
@@ -81,6 +86,7 @@
    	/* disable M-Mode interrupt */
         	write_csr(mie, 0);

+		if (0) {
    	long menvcfg_val = read_csr(menvcfg);
    	menvcfg_val |= ENVCFG_CBZE;
    	menvcfg_val |= ENVCFG_CBCFE;
@@ -91,6 +97,7 @@
    	printk(BIOS_DEBUG, "run_payload() envcfg: 0x%lx\n", menvcfg_val);

write_csr(menvcfg, menvcfg_val);
+		}

/* save stack to mscratch so trap_entry can use that as exception stack */
    	write_csr(mscratch, MACHINE_STACK_TOP());
@@ -108,6 +115,7 @@
    }

printk(BIOS_DEBUG, "run_payload(%p, %p) mstatus: 0x%lx\n", doit, fdt, status);
+	mdelay(5000);

write_csr(mstatus, status);
    write_csr(mepc, doit);
diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c
index ee39ac4..68dcc0f 100644
--- a/src/arch/riscv/pmp.c
+++ b/src/arch/riscv/pmp.c
@@ -96,6 +96,7 @@
    	new = (old & ~((uintptr_t)0xff << shift))
    		| ((cfg & 0xff) << shift);
    	write_csr(pmpcfg0, new);
+		printk(BIOS_EMERG, "%s: cfg %lx old %lx new %lx\n", __func__, cfg, old, new);
    	break;
    case 1:
    	old = read_csr(pmpcfg2);
@@ -105,8 +106,10 @@
    	break;
    }
 #endif
-	if (read_pmpcfg(idx) != cfg)
-		die("write pmpcfg failure!");
+	if (read_pmpcfg(idx) != cfg) {
+		printk(BIOS_EMERG, "%s: read(%d) is %lx, not %lx\n", __func__, idx, read_pmpcfg(idx), cfg);
+		//die("write pmpcfg failure!");
+	}
 }

/* helper function used to read pmpaddr[idx] */
@@ -202,8 +205,10 @@
    	write_csr(pmpaddr15, val);
    	break;
    }
-	if (read_pmpaddr(idx) != val)
-		die("write pmpaddr failure");
+	if (read_pmpaddr(idx) != val){
+		printk(BIOS_EMERG, "%s: read(%d) is %lx, not %lx\n", __func__, idx, read_pmpaddr(idx), val);
+		//die("write pmpaddr failure");
+	}
 }

/* Generate a PMP configuration of type NA4/NAPOT */
@@ -212,7 +217,14 @@
 {
    pmpcfg_t p;
    flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L);
-	p.cfg = flags | (size > GRANULE ? PMP_NAPOT : PMP_NA4);
+	if (size > GRANULE) {
+		p.cfg = flags | PMP_NAPOT;
+		p.previous_address = 0;
+		p.address = (base + (size / 2 - 1)) >> PMP_SHIFT;
+		return p;
+	}
+
+	p.cfg = flags | PMP_NA4;
    p.previous_address = 0;
    p.address = (base + (size / 2 - 1)) >> PMP_SHIFT;
    return p;
@@ -277,6 +289,7 @@
 /* reset PMP setting */
 void reset_pmp(void)
 {
+	printk(BIOS_EMERG, "%s: start\n", __func__);
    for (int i = 0; i < pmp_entries_num(); i++) {
    	if (read_pmpcfg(i) & PMP_L)
    		die("Some PMP configurations are locked "
@@ -284,6 +297,7 @@
    	write_pmpcfg(i, 0);
    	write_pmpaddr(i, 0);
    }
+	printk(BIOS_EMERG, "%s: done\n", __func__);
 }

/* set up PMP record */
@@ -292,6 +306,7 @@
    pmpcfg_t p;
    int is_range, n;

+	printk(BIOS_EMERG, "%s: start base %lx size %lx flags %lx\n", __func__, base, size, flags);
    p = generate_pmp(base, size, flags);
    is_range = ((p.cfg & PMP_A) == PMP_TOR);

@@ -300,9 +315,12 @@
    write_pmpaddr(n, p.address);
    if (is_range)
    	write_pmpaddr(n - 1, p.previous_address);
+	printk(BIOS_EMERG, "%s: p.cfg is %lx\n", __func__, p.cfg);
    write_pmpcfg(n, p.cfg);

mask_pmp_entry_used(n);
    if (is_range)
    	mask_pmp_entry_used(n - 1);
+	printk(BIOS_EMERG, "%s: done\n", __func__);
 }
+
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 9f51618..dbfbf49 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -53,6 +53,7 @@

// Enable all user/supervisor-mode counters
    write_csr(mcounteren, 7);
+	return;
    write_csr(scounteren, 7);

// Enable FPU, if available