Bora Guvendik (bora.guvendik@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18107
-gerrit
commit fa28608c185eeb6f6ef98811683ee0cc39724a5a Author: Bora Guvendik bora.guvendik@intel.com Date: Wed Jan 4 16:51:31 2017 -0800
Add a lock with timeout
In case something goes wrong on one of the cpus, add the ability to use a lock with timeout so that other cpus don't wait forever. Turn lock and release into apis
BUG=chrome-os-partner:59875 BRANCH=reef TEST=None
Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- src/cpu/x86/mp_init.c | 21 +++++++++++++++++++-- src/include/cpu/x86/mp.h | 6 ++++++ 2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c989963..f137ede 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -138,7 +138,7 @@ struct cpu_map { /* Keep track of APIC and device structure for each CPU. */ static struct cpu_map cpus[CONFIG_MAX_CPUS];
-static inline void barrier_wait(atomic_t *b) +inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) { asm ("pause"); @@ -146,7 +146,24 @@ static inline void barrier_wait(atomic_t *b) mfence(); }
-static inline void release_barrier(atomic_t *b) +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms) +{ + struct mono_time current, end; + + timer_monotonic_get(¤t); + end = current; + mono_time_add_msecs(&end, timeout_ms); + + while (atomic_read(b) == 0) { + timer_monotonic_get(¤t); + if (mono_time_after(¤t, &end)) + break; + asm ("pause"); + } + mfence(); +} + +inline void release_barrier(atomic_t *b) { mfence(); atomic_set(b, 1); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b9b4d57..113ed84 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -151,4 +151,10 @@ void smm_initiate_relocation_parallel(void); /* Send SMI to self with single execution. */ void smm_initiate_relocation(void);
+inline void barrier_wait(atomic_t *b); + +inline void release_barrier(atomic_t *b); + +inline void barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms); + #endif /* _X86_MP_H_ */