Change in coreboot[master]: soc/intel/icl: enable common CPU code

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 )

Change subject: soc/intel/icl: enable common CPU code
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/romst... 
File src/soc/intel/icelake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/romst... 
PS2, Line 59: 	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
This already configures VMX in FSP and set the feature lock bit (FC_LOCK MSR).

In FSP (CNL, TGL, so I expect ICL to be the same) is enabled and fc is locked only if SkipMpInit=0 && VmxEnable=1. Since ICL coreboot dropped SkipMpInit and switched to MP PPI usage, we have two options here:

1) Set FSP option VmxEnable from Kconfig as done above and do nothing else in coreboot
2) Set FSP option VmxEnable=0 statically and call set_vmx_and_lock() from cpu/intel/common