HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38100 )
Change subject: mainboard/amd/parmer: Drop boards with ROMCC_BOOTBLOCK ......................................................................
mainboard/amd/parmer: Drop boards with ROMCC_BOOTBLOCK
ROMCC_BOOTBLOCK is no more. Drop unsupported or/and unmaintained boards.
Change-Id: I77a9968bec481190e64f08f52b61ae76547e1c0d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M Documentation/AMD-S3.txt D src/mainboard/amd/parmer/BiosCallOuts.c D src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/Kconfig.name D src/mainboard/amd/parmer/Makefile.inc D src/mainboard/amd/parmer/OemCustomize.c D src/mainboard/amd/parmer/OptionsIds.h D src/mainboard/amd/parmer/acpi/gpe.asl D src/mainboard/amd/parmer/acpi/mainboard.asl D src/mainboard/amd/parmer/acpi/routing.asl D src/mainboard/amd/parmer/acpi/sata.asl D src/mainboard/amd/parmer/acpi/si.asl D src/mainboard/amd/parmer/acpi/sleep.asl D src/mainboard/amd/parmer/acpi/superio.asl D src/mainboard/amd/parmer/acpi/thermal.asl D src/mainboard/amd/parmer/acpi/usb_oc.asl D src/mainboard/amd/parmer/acpi_tables.c D src/mainboard/amd/parmer/board_info.txt D src/mainboard/amd/parmer/buildOpts.c D src/mainboard/amd/parmer/cmos.layout D src/mainboard/amd/parmer/devicetree.cb D src/mainboard/amd/parmer/dsdt.asl D src/mainboard/amd/parmer/irq_tables.c D src/mainboard/amd/parmer/mainboard.c D src/mainboard/amd/parmer/mptable.c D src/mainboard/amd/parmer/romstage.c 26 files changed, 4 insertions(+), 2,096 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38100/1
diff --git a/Documentation/AMD-S3.txt b/Documentation/AMD-S3.txt index bfabcbe..426e741 100644 --- a/Documentation/AMD-S3.txt +++ b/Documentation/AMD-S3.txt @@ -106,11 +106,11 @@ non-volatile storage at cold boot stage. What data need to be save are provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets the VolatileStorage and NvStorage, which are where the data are -located. It is the wrappers's responsibility to save the data.[3][4] +located. It is the wrappers's responsibility to save the data.[3] Currently, the wrappers allocate a CBFS modules in BIOS image. To do that, the wrapper needs to have the ability to write flash chips. It is not as comprehensive as flashrom. But for the SST chip on Parmer, -MX chip on Thather, coreboot works well.[5] +MX chip on Thather, coreboot works well.[4]
2. OS goes in S3. For Linux, besides the kernel needs to do some saving, most distributions @@ -148,6 +148,5 @@ ========= [1] ACPI40a, http://www.acpi.info/spec40a.htm [2] coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ -[3] coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c -[4] coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c -[5] coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c +[3] coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c +[4] coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c deleted file mode 100644 index 0c54211..0000000 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> -#include <stdlib.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Parmer Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Parmer Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control. the recommand way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ - FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig deleted file mode 100644 index ae024dd..0000000 --- a/src/mainboard/amd/parmer/Kconfig +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config BOARD_AMD_PARMER - def_bool n - -if BOARD_AMD_PARMER - -config BOARD_SPECIFIC_OPTIONS - def_bool y - #select ROMCC_BOOTBLOCK - select CPU_AMD_AGESA_FAMILY15_TN - select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN - select SOUTHBRIDGE_AMD_AGESA_HUDSON - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "amd/parmer" - -config MAINBOARD_PART_NUMBER - string - default "Parmer" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,9900" - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_PARMER diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name deleted file mode 100644 index 0771468..0000000 --- a/src/mainboard/amd/parmer/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -#config BOARD_AMD_PARMER -# bool"Parmer" diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc deleted file mode 100644 index f8895fa..0000000 --- a/src/mainboard/amd/parmer/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c deleted file mode 100644 index 2eed8b2..0000000 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - - -/* - * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) - * - * Lane Id - * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 - * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 - * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 - * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 - * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 - * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 - * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 - * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 - * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI - * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI - * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI - * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI - * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI - * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI - * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI - * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI - * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI - * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI - * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI - * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI - * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI - * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI - * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI - * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI - * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) - * 25 DP0_TX[P,N]1 - * 26 DP0_TX[P,N]2 - * 27 DP0_TX[P,N]3 - * 28 DP1_TX[P,N]0 - * 29 DP1_TX[P,N]1 - * 30 DP1_TX[P,N]2 - * 31 DP1_TX[P,N]3 - * 32 DP2_TX[P,N]0 - * 33 DP2_TX[P,N]1 - * 34 DP2_TX[P,N]2 - * 35 DP2_TX[P,N]3 - * 36 DP2_TX[P,N]4 - * 37 DP2_TX[P,N]5 - * 38 DP2_TX[P,N]6 - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 1) - }, - - /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0) - }, -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h deleted file mode 100644 index eaf2442..0000000 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl deleted file mode 100644 index 32d5a2a..0000000 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope(_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\_GPE\_L00\n") */ - Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\_GPE\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\_GPE\_L09\n") */ - /* Notify (_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\_GPE\_L0B\n") */ - Notify(_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\_GPE\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\_GPE\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\_GPE\_L18\n") */ - Notify(_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\_GPE\_L1B\n") */ - Notify(_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/parmer/acpi/mainboard.asl b/src/mainboard/amd/parmer/acpi/mainboard.asl deleted file mode 100644 index fb75289..0000000 --- a/src/mainboard/amd/parmer/acpi/mainboard.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* AcpiGpe0Blk */ - OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, - } diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl deleted file mode 100644 index 56bd465..0000000 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ /dev/null @@ -1,320 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - /* Routing is in System Bus scope */ - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 Pcie Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - }) diff --git a/src/mainboard/amd/parmer/acpi/sata.asl b/src/mainboard/amd/parmer/acpi/sata.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/parmer/acpi/sata.asl +++ /dev/null diff --git a/src/mainboard/amd/parmer/acpi/si.asl b/src/mainboard/amd/parmer/acpi/si.asl deleted file mode 100644 index ff0c3cf..0000000 --- a/src/mainboard/amd/parmer/acpi/si.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - Scope(_SI) { - Method(_SST, 1) { - /* DBGO("\_SI\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl deleted file mode 100644 index d516cce..0000000 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* _PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(_PTS, 1) { - /* DBGO("\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(_SB.SBRI, 0x13)) { - * Store(0,_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - - Store (0x07, UPWS) -} /* End Method(_PTS) */ - -/* -* _BFS OEM Back From Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* -none- -*/ -Method(_BFS, 1) { - /* DBGO("\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ -} - -/* -* _WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(_WAK, 1) { - /* DBGO("\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,USBS) - - Return(WKST) -} /* End Method(_WAK) */ diff --git a/src/mainboard/amd/parmer/acpi/superio.asl b/src/mainboard/amd/parmer/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/parmer/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/amd/parmer/acpi/thermal.asl b/src/mainboard/amd/parmer/acpi/thermal.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/amd/parmer/acpi/thermal.asl +++ /dev/null diff --git a/src/mainboard/amd/parmer/acpi/usb_oc.asl b/src/mainboard/amd/parmer/acpi/usb_oc.asl deleted file mode 100644 index f5d6980..0000000 --- a/src/mainboard/amd/parmer/acpi/usb_oc.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c deleted file mode 100644 index fd59a3a..0000000 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/ioapic.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/parmer/board_info.txt b/src/mainboard/amd/parmer/board_info.txt deleted file mode 100644 index 4ed37bc..0000000 --- a/src/mainboard/amd/parmer/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: DB-FS1r2 (Parmer) -Category: eval -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c deleted file mode 100644 index 7ff6caa..0000000 --- a/src/mainboard/amd/parmer/buildOpts.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - */ - -#include <stdlib.h> -#include <AGESA.h> - -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE - -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE - -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE - -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 - -GPIO_CONTROL parmer_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout deleted file mode 100644 index e1dbd9a..0000000 --- a/src/mainboard/amd/parmer/cmos.layout +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb deleted file mode 100644 index aad3413..0000000 --- a/src/mainboard/amd/parmer/devicetree.cb +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn - - chip southbridge/amd/agesa/hudson - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SMBUS - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family15tn - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl deleted file mode 100644 index 77bd704..0000000 --- a/src/mainboard/amd/parmer/dsdt.asl +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (_PR) */ - #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> - - /* Describe the supported Sleep States for this Southbridge */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ - #include "acpi/sleep.asl" - - Scope(_SB) { - /* global utility methods expected within the _SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the _SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End Scope(_SB) */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" - - /* Define the System Indicators for the platform */ - #include "acpi/si.asl" - -} -/* End of ASL file */ diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c deleted file mode 100644 index 530c132..0000000 --- a/src/mainboard/amd/parmer/irq_tables.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "write_pirq_routing_table done.\n"); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c deleted file mode 100644 index 0051d74..0000000 --- a/src/mainboard/amd/parmer/mainboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> - -/************************************************* - * enable the dedicated function in parmer board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c deleted file mode 100644 index c2b9f98..0000000 --- a/src/mainboard/amd/parmer/mptable.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c deleted file mode 100644 index 6366c4e..0000000 --- a/src/mainboard/amd/parmer/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - - /* For serial port option, plug-in card on LPC. */ - pci_write_config32(dev, 0x44, 0xff03ffd5); -}
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38100 )
Change subject: mainboard/amd/parmer: Drop boards with ROMCC_BOOTBLOCK ......................................................................
Patch Set 1: Code-Review-1
Switched away amd/parmer from ROMCC_BOOTBLOCK at CB:37744 , please review.
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38100 )
Change subject: mainboard/amd/parmer: Drop boards with ROMCC_BOOTBLOCK ......................................................................
Abandoned
-
HAOUAS Elyes (Code Review) -
Mike Banon (Code Review)