Change in coreboot[master]: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/...
Ryback Hung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. ......................................................................
configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO.
It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload.
Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass A src/mainboard/ocp/sonorapass/Kconfig A src/mainboard/ocp/sonorapass/Kconfig.name A src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/acpi/platform.asl A src/mainboard/ocp/sonorapass/board.fmd A src/mainboard/ocp/sonorapass/board_info.txt A src/mainboard/ocp/sonorapass/bootblock.c A src/mainboard/ocp/sonorapass/devicetree.cb A src/mainboard/ocp/sonorapass/dsdt.asl 10 files changed, 320 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/1
diff --git a/configs/builder/config.ocp.sonorapass b/configs/builder/config.ocp.sonorapass new file mode 100644 index 0000000..c05dce2 --- /dev/null +++ b/configs/builder/config.ocp.sonorapass @@ -0,0 +1,21 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.sonorapass + +CONFIG_VENDOR_OCP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="site-local/cedarisland_crb/ucode-05-06-5a" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/cedarisland_crb/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/cedarisland_crb/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/cedarisland_crb/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/sonorapass/me.bin" +CONFIG_IFD_BIN_PATH="site-local/sonorapass/descriptor.bin" +CONFIG_CONSOLE_SERIAL_57600=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/linuxboot_uroot_ttys0" +CONFIG_LINUX_COMMAND_LINE="earlyprintk=uart8250,io,0x3f8,57600n1 console=uart8250,io,0x3f8,57600n1 loglevel=7" diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig new file mode 100644 index 0000000..34adf5f --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_OCP_SONORAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select IPMI_KCS + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default "ocp/sonorapass" + +config MAINBOARD_PART_NUMBER + string + default "SonoraPass" + +config MAINBOARD_FAMILY + string + default "SonoraPass" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name new file mode 100644 index 0000000..90e7f3d --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_SONORAPASS + bool "SonoraPass" diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl new file mode 100644 index 0000000..75c1b92 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/acpi/platform.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd new file mode 100644 index 0000000..e28bcf0 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board.fmd @@ -0,0 +1,10 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x2fd8000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fc5000 + } + FMAP@0x03000000 0x800 + RW_MRC_CACHE@0x3000800 0x10000 + COREBOOT(CBFS)@0x3010800 +} diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt new file mode 100644 index 0000000..bbf3ee9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: SonoraPass +Category: server +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c new file mode 100644 index 0000000..06f45c9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/bootblock.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F + +void bootblock_mainboard_early_init(void) +{ + struct config_data port80[] = { + /* {Type, base, reg, and, or} */ + /* Set command source of GPIOH to LPC */ + {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000}, + {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000}, + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* Program GPIOH multi-function to GPIO */ + {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000}, + /* Program GPIOH as output */ + {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000}, + /* Set snooping address#0 as 80h */ + {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080}, + /* Enable snooping address#0 */ + {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001}, + /* Enable GPIO device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE}, + /* Select GPIOH for port80 GPIO */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL}, + /* Disable GPIO Device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY} + }; + struct config_data uart[] = { + /* {Type, base, reg, and, or} */ + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* SERIAL PORT1 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + /* SERIAL PORT2 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + }; + + /* Enable COM1 only */ + pcr_write32(PID_DMI, 0x2770, 0); + pcr_write32(PID_DMI, 0x2774, 1); + + /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + aspeed_early_config(ASPEED_CONFIG_INDEX, port80, ARRAY_SIZE(port80)); + + /* Init UART */ + aspeed_early_config(ASPEED_CONFIG_INDEX, uart, ARRAY_SIZE(uart)); +} diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb new file mode 100644 index 0000000..fff834a --- /dev/null +++ b/src/mainboard/ocp/sonorapass/devicetree.cb @@ -0,0 +1,53 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + end + + end +end diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl new file mode 100644 index 0000000..3dc45d5 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +#include <soc/iomap.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (_SB) + { + Device (PCI0) + { + #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> + #include <soc/intel/common/block/acpi/acpi/lpc.asl> + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. ......................................................................
Patch Set 1:
(72 comments)
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... File src/mainboard/ocp/sonorapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 23: struct config_data port80[] = { please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 24: /* {Type, base, reg, and, or} */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 24: /* {Type, base, reg, and, or} */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 24: /* {Type, base, reg, and, or} */ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 25: /* Set command source of GPIOH to LPC */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 26: {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 26: {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 27: {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 27: {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 28: /* Unlock SCU Registers */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 29: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 29: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 30: /* Program GPIOH multi-function to GPIO */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 31: {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 31: {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 32: /* Program GPIOH as output */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 33: {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 33: {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 34: /* Set snooping address#0 as 80h */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 35: {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 35: {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 36: /* Enable snooping address#0 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 37: {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 37: {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 38: /* Enable GPIO device */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 39: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 39: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 40: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 40: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 41: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 41: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 42: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 42: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 43: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 43: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 44: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 44: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 45: /* Select GPIOH for port80 GPIO */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 46: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 46: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 47: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 47: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 48: /* Disable GPIO Device */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 49: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 49: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 50: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 50: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 51: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 51: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 52: {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 52: {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 53: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY} code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 53: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY} please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 55: struct config_data uart[] = { please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 56: /* {Type, base, reg, and, or} */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 56: /* {Type, base, reg, and, or} */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 56: /* {Type, base, reg, and, or} */ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 57: /* Unlock SCU Registers */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 58: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 58: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 59: /* SERIAL PORT1 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 60: {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 60: {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 61: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 61: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 62: /* SERIAL PORT2 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 63: {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 63: {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 64: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 64: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 78: aspeed_early_config(ASPEED_CONFIG_INDEX, port80, ARRAY_SIZE(port80)); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/40334/1/src/mainboard/ocp/sonorapas... PS1, Line 81: aspeed_early_config(ASPEED_CONFIG_INDEX, uart, ARRAY_SIZE(uart)); please, no spaces at the start of a line
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40334
to look at the new patch set (#2).
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO.
It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload.
Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass A src/mainboard/ocp/sonorapass/Kconfig A src/mainboard/ocp/sonorapass/Kconfig.name A src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/acpi/platform.asl A src/mainboard/ocp/sonorapass/board.fmd A src/mainboard/ocp/sonorapass/board_info.txt A src/mainboard/ocp/sonorapass/bootblock.c A src/mainboard/ocp/sonorapass/devicetree.cb A src/mainboard/ocp/sonorapass/dsdt.asl 10 files changed, 320 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/2
Ryback Hung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
Patch Set 2:
Preliminary platform porting for SonoraPass PO.
Ryback Hung has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
Removed reviewer Patrick Georgi.
Ryback Hung has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
Removed reviewer Martin Roth.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
Patch Set 2:
(14 comments)
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@12 PS2, Line 12: Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b please add Signed-off-by line in commit message
https://review.coreboot.org/c/coreboot/+/40334/2/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
PS2: It is better to do this in a separate patch. See CB:39783
https://review.coreboot.org/c/coreboot/+/40334/2/configs/builder/config.ocp.... PS2, Line 12: cedarisland_crb sonorapass
https://review.coreboot.org/c/coreboot/+/40334/2/configs/builder/config.ocp.... PS2, Line 13: cedarisland_crb sonorapass
https://review.coreboot.org/c/coreboot/+/40334/2/configs/builder/config.ocp.... PS2, Line 14: cedarisland_crb sonorapass
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... File src/mainboard/ocp/sonorapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 16: tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 17: tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 18: tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 19: tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 25: please use tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 26: please use tabs in all such cases
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 78: tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 80: tab
https://review.coreboot.org/c/coreboot/+/40334/2/src/mainboard/ocp/sonorapas... PS2, Line 81: tab
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@7 PS2, Line 7: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. : src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. You should split it into 2 different patches for example Cedar Island board: CB:39783 and CB:39714
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@10 PS2, Line 10: It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload. from https://www.coreboot.org/Git:
1. The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary 2. The second line is empty (no whitespace at all) 3. The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters. 4. The next line is empty (no whitespace at all) 5. A Change-Id: line to let gerrit track this logical change 6. A Signed-off-by: line according to the development guidelines
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO. ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@10 PS2, Line 10: It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload.
from https://www.coreboot.org/Git: […]
The maximum is actually 72
Hello build bot (Jenkins), Andrey Petrov, David Hendricks, Jonathan Zhang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40334
to look at the new patch set (#3).
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
configs: Add builder config to create a working Sonora Pass
Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b Signed-off-by: ryback.hung ryback.hung%quantatw.com@gtempaccount.com --- A configs/builder/config.ocp.sonorapass 1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/3
Ryback Hung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 3:
Patch Set 2:
(14 comments)
It's done to separate patch.
Ryback Hung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 3:
(3 comments)
Already followed comment to modify accordingly.
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@7 PS2, Line 7: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. : src/mainboard/ocp/sonorapass/*.*: Preliminary platform porting for SonoraPass PO.
You should split it into 2 different patches […]
Done
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@10 PS2, Line 10: It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload.
The maximum is actually 72
Done
https://review.coreboot.org/c/coreboot/+/40334/2//COMMIT_MSG@12 PS2, Line 12: Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b
please add Signed-off-by line in commit message
Done
Hello build bot (Jenkins), Andrey Petrov, David Hendricks, Jonathan Zhang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40334
to look at the new patch set (#4).
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
configs: Add builder config to create a working Sonora Pass
Sgined-off-by: ryback.hung ryback.hung@quantatw.com Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass 1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/4
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40334/5//COMMIT_MSG@9 PS5, Line 9: Sgined Typo
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: uart8250,io,0x3f8 you really do not want to hard the port here. I think it should be: console=ttyS0,57600n1.
Also: on SonoraPass we have 2 useful SIO ports: com1 that is wired to debug header and com2 that is wired to SOL. this should be noted int the comment below.
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: earlyprintk=uart8250,io,0x3f8 please note: this syntax is not correct. This is extremely confusing, and must be fixed. Since earlyprintk is not specified correctly and under certain conditions kernel might crash before regular console becomes operational, this is really ugly problem.
what we want instead is: earlyprintk=serial,0x3f8,57600n1 Another option: earlyprintk=serial,ttyS0,57600n1 which is better.
https://www.kernel.org/doc/html/v4.14/admin-guide/kernel-parameters.html
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: earlyprintk=uart8250,io,0x3f8
please note: this syntax is not correct. This is extremely confusing, and must be fixed. […]
coreboot uses 115200 by default, wouldn't it make more sense to use the same value for earlyprintk? Or is this a different UART than the one used for coreboot?
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: earlyprintk=uart8250,io,0x3f8
coreboot uses 115200 by default, wouldn't it make more sense to use the same value for earlyprintk? […]
for OCP hardware you have two logging options: debug card that is usually wired to serial port #1, and SOL which is wired into virtual port of bmc chip, so that is port #2. For SOL port it is set to 57600 in openBMC. So that is probably why
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: earlyprintk=uart8250,io,0x3f8
for OCP hardware you have two logging options: debug card that is usually wired to serial port #1, a […]
Angel, see above: `CONFIG_CONSOLE_SERIAL_57600=y`.
That OpenBMC configuration/requirement slows down the boot. :/
Hello build bot (Jenkins), Andrey Petrov, David Hendricks, Jonathan Zhang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40334
to look at the new patch set (#9).
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
configs: Add builder config to create a working Sonora Pass
Signed-off-by: Ryback Hung ryback.hung%quantatw.com@gtempaccount.com Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass 1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/9
Ryback Hung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 10:
(2 comments)
It's done for 'earlyprintk=serial,ttyS0,57600n1' and 'console=ttyS0,57600n1'.
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: earlyprintk=uart8250,io,0x3f8
Angel, see above: `CONFIG_CONSOLE_SERIAL_57600=y`. […]
Done
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: uart8250,io,0x3f8
you really do not want to hard the port here. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... File configs/builder/config.ocp.sonorapass:
https://review.coreboot.org/c/coreboot/+/40334/8/configs/builder/config.ocp.... PS8, Line 21: earlyprintk=uart8250,io,0x3f8
Done
D'oh, missed that. Sorry for the noise.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40334 )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40334/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40334/10//COMMIT_MSG@7 PS10, Line 7: Sonora Pass Sonora Pass was dropped in CB:42948
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40334?usp=email )
Change subject: configs: Add builder config to create a working Sonora Pass ......................................................................
Abandoned
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Andrey Petrov (Code Review) -
Angel Pons (Code Review)
-
build bot (Jenkins) (Code Review)
-
Christian Walter (Code Review)
-
Maxim Polyakov (Code Review)
-
Paul Menzel (Code Review)
-
Ryback Hung (Code Review)
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Stefan Reinauer (Code Review)