72 comments:
File src/mainboard/ocp/sonorapass/bootblock.c:
Patch Set #1, Line 23: struct config_data port80[] = {
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Patch Set #1, Line 24: /* {Type, base, reg, and, or} */
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Patch Set #1, Line 24: /* {Type, base, reg, and, or} */
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Patch Set #1, Line 24: /* {Type, base, reg, and, or} */
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Patch Set #1, Line 25: /* Set command source of GPIOH to LPC */
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Patch Set #1, Line 26: {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000},
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Patch Set #1, Line 26: {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000},
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Patch Set #1, Line 27: {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000},
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Patch Set #1, Line 27: {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000},
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Patch Set #1, Line 28: /* Unlock SCU Registers */
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Patch Set #1, Line 29: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8},
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Patch Set #1, Line 29: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8},
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Patch Set #1, Line 30: /* Program GPIOH multi-function to GPIO */
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Patch Set #1, Line 31: {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000},
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Patch Set #1, Line 31: {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000},
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Patch Set #1, Line 32: /* Program GPIOH as output */
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Patch Set #1, Line 33: {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000},
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Patch Set #1, Line 33: {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000},
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Patch Set #1, Line 34: /* Set snooping address#0 as 80h */
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Patch Set #1, Line 35: {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080},
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Patch Set #1, Line 35: {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080},
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Patch Set #1, Line 36: /* Enable snooping address#0 */
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Patch Set #1, Line 37: {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001},
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Patch Set #1, Line 37: {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001},
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Patch Set #1, Line 38: /* Enable GPIO device */
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Patch Set #1, Line 39: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY},
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Patch Set #1, Line 39: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY},
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Patch Set #1, Line 40: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY},
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Patch Set #1, Line 40: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY},
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Patch Set #1, Line 41: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL},
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Patch Set #1, Line 41: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL},
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Patch Set #1, Line 42: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO},
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Patch Set #1, Line 42: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO},
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Patch Set #1, Line 43: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG},
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Patch Set #1, Line 43: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG},
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Patch Set #1, Line 44: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE},
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Patch Set #1, Line 44: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE},
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Patch Set #1, Line 45: /* Select GPIOH for port80 GPIO */
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Patch Set #1, Line 46: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL},
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Patch Set #1, Line 46: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL},
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Patch Set #1, Line 47: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL},
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Patch Set #1, Line 47: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL},
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Patch Set #1, Line 48: /* Disable GPIO Device */
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Patch Set #1, Line 49: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL},
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Patch Set #1, Line 49: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL},
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Patch Set #1, Line 50: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO},
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Patch Set #1, Line 50: {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO},
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Patch Set #1, Line 51: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG},
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Patch Set #1, Line 51: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG},
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Patch Set #1, Line 52: {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE},
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Patch Set #1, Line 52: {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE},
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Patch Set #1, Line 53: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY}
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Patch Set #1, Line 53: {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY}
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Patch Set #1, Line 55: struct config_data uart[] = {
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Patch Set #1, Line 56: /* {Type, base, reg, and, or} */
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Patch Set #1, Line 56: /* {Type, base, reg, and, or} */
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Patch Set #1, Line 56: /* {Type, base, reg, and, or} */
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Patch Set #1, Line 57: /* Unlock SCU Registers */
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Patch Set #1, Line 58: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8},
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Patch Set #1, Line 58: {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8},
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Patch Set #1, Line 59: /* SERIAL PORT1 */
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Patch Set #1, Line 60: {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000},
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Patch Set #1, Line 60: {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000},
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Patch Set #1, Line 61: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000},
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Patch Set #1, Line 61: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000},
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Patch Set #1, Line 62: /* SERIAL PORT2 */
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Patch Set #1, Line 63: {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000},
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Patch Set #1, Line 63: {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000},
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Patch Set #1, Line 64: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000},
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Patch Set #1, Line 64: {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000},
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Patch Set #1, Line 78: aspeed_early_config(ASPEED_CONFIG_INDEX, port80, ARRAY_SIZE(port80));
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Patch Set #1, Line 81: aspeed_early_config(ASPEED_CONFIG_INDEX, uart, ARRAY_SIZE(uart));
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