Change in coreboot[master]: mb/google/volteer: Create APIs for USB-C DP alternate mode support

[Derek Huang (Code Review)]

Attention is currently required from: Zhuohao Lee, Brandon Breitenstein, Curtis Chen.
Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 )

Change subject: mb/google/volteer: Create APIs for USB-C DP alternate mode support
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Patch Set 5:

(4 comments)

Patchset:

PS5:
> Derek, is this a demo patch or a formal patch?

Yes, this is formal patch. changes in tcss.c are shared for TGL and ADL and mainboard functions can be reused by ADL projects.

It should not impact any existing TGL projects as ENABLE_TCSS_DISPLAY_DETECTION is not defined

File src/mainboard/google/volteer/mainboard.c:

https://review.coreboot.org/c/coreboot/+/57139/comment/9eb55a51_cf627ab2 
PS5, Line 27: DP_MODE_DELAY
> Why this is set to 1500? Does the EC spend 1500ms to apply the change?

I tested 3 different USB-C to HDMI dongles and one DP monitor. Only one of the dongle seems to be problematic and needs longer delay. The problematic dongle takes much more time (>3 seconds) to complete HPD notification. Maybe the better way is polling HPD status instead of hard-coded delay. I will update the CL to poll HPD status and remove the 1500ms delay

File src/soc/intel/common/block/tcss/tcss.c:

https://review.coreboot.org/c/coreboot/+/57139/comment/9b8410df_be85a8ad 
PS5, Line 195: 1, /* HPD=1 because hot-plug is not supported in pre-OS */
> Can't catch this. […]

I will update CL to poll HPD status until it become 1, so HPD level won't be hard-coded here.

However, the DP mux configuration must be done before FSP-S so we assume DP device is connected before boot. hot-plug in pre-OS environment is not supported

https://review.coreboot.org/c/coreboot/+/57139/comment/22a37bf4_42c474cc 
PS5, Line 295: WAIT_FOR_DISPLAYPORT_TIMEOUT
> How to decide this timeout value? Do you have the timing data for the normal display connection?

The time is for EC to finish PD Discovery SVIDs to identify the DP alternate (SVID=0xff01) mode supported by the connected device.

I check the timing in EC log, it take ~1 second from AP enter S0 to EC complete SVID discovery and identify DP device:

21-08-30 15:31:55.343 [9212.701873 power state 3 = S0, in 0x007f]
...
..
21-08-30 15:31:56.449 [9213.827271 C1: PE_INIT_VDM_SVIDs_Request]
21-08-30 15:31:56.484 C1: RECV 2c8f/2 [0]ff00a042 [1]ff010000
..

We configure DP mux in FspSiliconInit stage, ~0.8s is passed after boot, and we wait 1 second here so EC should complete Discovery SVID task