[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Bincai Liu, Hung-Te Lin, Jarried Lin, Jitao Shi, Yidi Lin.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email )

Change subject: soc/mediatek/mt8196: Add eDP driver
......................................................................

Patch Set 8: Code-Review+2

(9 comments)

File src/soc/mediatek/mt8196/dp_intf.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/16c1aacc_6709aac9?usp... :
PS7, Line 95: 0x20
> `0x20 << EXT_TG_DLY_LINE`

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/906dd603_30dc5819?usp... :
PS7, Line 100: if (dvo->gs_level >= MTK_DVO_GSL_MAX)
             : 		return;
> `assert(dvo->gs_level < MTK_DVO_GSL_MAX)`

Done

File src/soc/mediatek/mt8196/dptx.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/8a896ecc_a861a131?usp... :
PS7, Line 52: 					   u8 dpcd_adjust_req[DP_LANSE_ADJUST_SIZE])
> align

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/0ebdff38_9f8dac3f?usp... :
PS7, Line 70: DP_TRAIN_VOLTAGE_SWING_LEVEL_3
> DPTX_SWING3

Done

File src/soc/mediatek/mt8196/dptx_hal.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/339825de_9be18440?usp... :
PS7, Line 106: mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, 0x18);
             : 		mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, 0x6);
> Can we merge these into a single call? […]

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/717fae32_53fdd21f?usp... :
PS7, Line 290: dptx_hal_reset_swing_preemphasis_mt8196
> How about `dptx_hal_swing_emp_reset` (to be consistent with `dptx_hal_phyd_reset` below)?

Done

File src/soc/mediatek/mt8196/dptx_hal.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/0b4f97f3_5466f0cd?usp... :
PS8, Line 106: 		mtk_dp_phy_mask(mtk_dp, driving_offset[i], 0, EDP_TX_LN_VOLT_SWING_VAL_MASK |
Move mask to the next line.

File src/soc/mediatek/mt8196/include/soc/dptx_hal.h:

https://review.coreboot.org/c/coreboot/+/85949/comment/8bef6491_b65e494d?usp... :
PS7, Line 32: 				   u8 *preemphasis);
> align

Done

File src/soc/mediatek/mt8196/include/soc/dptx_reg.h:

https://review.coreboot.org/c/coreboot/+/85949/comment/a8ed68ef_8666a54b?usp... :
PS7, Line 198: DP_TRAIN_VOLTAGE_SWING_LEVEL_3
> Also duplicate of `DPTX_SWING3`.

Done