[L] Change in coreboot[main]: mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips

[Felix Held (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Varshit Pandya.

Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Varshit Pandya, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81101?usp=email

to look at the new patch set (#5).

The following approvals got outdated and were removed:
Code-Review+1 by Varshit Pandya, Verified+1 by build bot (Jenkins)

Change subject: mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
......................................................................

mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips

Add the stub MPIO chips that contain the PCIe engine configuration for
the external PCIe interfaces to the devicetree. Birman's
port_descriptors_phoenix.c was used as a reference. The static
configuration in the devicetree assumes that the default WLAN0_WWAN0 is
selected; for the other cases we'll still need to fix up things
accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still
need to be handled in a follow-up patch. Since openSIL currently doesn't
use the info from the gpio_group struct element, but deasserts both PCIe
reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip
configuration in the devicetree.

Signed-off-by: Felix Held 
Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb
---
M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
M src/soc/amd/phoenix/Kconfig
R src/soc/amd/phoenix/chipset_fsp.cb
A src/soc/amd/phoenix/chipset_opensil.cb
4 files changed, 239 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/81101/5