Change in coreboot[master]: treewide: capitalize 'USB' - coreboot-gerrit

24 Feb 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39100 )
Change subject: treewide: capitalize 'USB'
......................................................................
treewide: capitalize 'USB'
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
M payloads/libpayload/drivers/udc/chipidea.c
M payloads/libpayload/drivers/udc/chipidea_priv.h
M payloads/libpayload/drivers/usb/ehci.c
M payloads/libpayload/drivers/usb/usb.c
M payloads/libpayload/drivers/usb/usbmsc.c
M payloads/libpayload/include/libpayload.h
M payloads/libpayload/include/usb/usb.h
M src/drivers/usb/ehci_debug.c
M src/mainboard/google/butterfly/early_init.c
M src/mainboard/google/link/early_init.c
M src/mainboard/google/mistral/mainboard.c
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/parrot/early_init.c
M src/mainboard/google/stout/early_init.c
M src/mainboard/intel/emeraldlake2/early_init.c
M src/mainboard/intel/harcuvar/hsio.h
M src/mainboard/kontron/ktqm77/early_init.c
M src/mainboard/lenovo/t430s/variants/t431s/romstage.c
M src/mainboard/samsung/lumpy/early_init.c
M src/mainboard/samsung/stumpy/early_init.c
M src/mainboard/scaleway/tagada/hsio.h
M src/soc/intel/apollolake/chip.c
M src/soc/intel/common/block/xhci/elog.c
M src/soc/mediatek/common/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/intel/i82801gx/early_init.c
M util/uio_usbdebug/uio_usbdebug_intel.c
27 files changed, 46 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39100/1

diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c
index 702cd6e..d8d02f2 100644
--- a/payloads/libpayload/drivers/udc/chipidea.c
+++ b/payloads/libpayload/drivers/udc/chipidea.c
@@ -81,7 +81,7 @@
    memcpy(&this->device_descriptor, dd, sizeof(*dd));
if (p->qhlist == NULL)
-		die("failed to allocate memory for usb device mode");
+		die("failed to allocate memory for USB device mode");
memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS);
@@ -102,7 +102,7 @@
    p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS;
do {
-		debug("waiting for usb phy clk valid: %x\n",
+		debug("waiting for USB phy clk valid: %x\n",
    		readl(&p->opreg->susp_ctrl));
    	mdelay(1);
    } while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0);
diff --git a/payloads/libpayload/drivers/udc/chipidea_priv.h b/payloads/libpayload/drivers/udc/chipidea_priv.h
index ede97ab..82870c3 100644
--- a/payloads/libpayload/drivers/udc/chipidea_priv.h
+++ b/payloads/libpayload/drivers/udc/chipidea_priv.h
@@ -47,7 +47,7 @@
    uint32_t portsc; // 0x174
    uint32_t pad178[15];
    uint32_t devlc; // 0x1b4
-		/* 25:26: host-desired usb version
+		/* 25:26: host-desired USB version
    	 * 23: force full speed */
    uint32_t pad1b8[16];
    uint32_t usbmode; // 0x1f8
diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c
index 1cfa8bb..bf8a5ea 100644
--- a/payloads/libpayload/drivers/usb/ehci.c
+++ b/payloads/libpayload/drivers/usb/ehci.c
@@ -291,7 +291,7 @@
/* Memory barrier to ensure that all memory accesses before we set the
     * async schedule are complete. It was observed especially in the case of
-	 * arm64, that netboot and usb stuff resulted in lots of errors possibly
+	 * arm64, that netboot and USB stuff resulted in lots of errors possibly
     * due to CPU reordering. Hence, enforcing strict CPU ordering.
     */
    mb();
diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c
index d98fd9e..942e1b1 100644
--- a/payloads/libpayload/drivers/usb/usb.c
+++ b/payloads/libpayload/drivers/usb/usb.c
@@ -634,14 +634,14 @@
/*
  * Should be called by the hub drivers whenever a physical detach occurs
- * and can be called by usb class drivers if they are unsatisfied with a
+ * and can be called by USB class drivers if they are unsatisfied with a
  * malfunctioning device.
  */
 void
 usb_detach_device(hci_t *controller, int devno)
 {
    /* check if device exists, as we may have
-	   been called yet by the usb class driver */
+	   been called yet by the USB class driver */
    if (controller->devices[devno]) {
    	controller->devices[devno]->destroy (controller->devices[devno]);
diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c
index 50fd24b..ed7ad1a 100755
--- a/payloads/libpayload/drivers/usb/usbmsc.c
+++ b/payloads/libpayload/drivers/usb/usbmsc.c
@@ -126,7 +126,7 @@
     * MSC commands can be
     *   successful,
     *   fail with proper response or
-	 *   fail totally, which results in detaching of the usb device
+	 *   fail totally, which results in detaching of the USB device
     *   and immediate cleanup of the usbdev_t structure.
     * In the latter case the caller has to make sure, that he won't
     * use the device any more.
@@ -703,14 +703,14 @@
    	return;
if (!prev_ready && msc->ready) {
-		usb_debug ("usb msc: not ready -> ready (lun %d)\n", msc->lun);
+		usb_debug ("USB msc: not ready -> ready (lun %d)\n", msc->lun);
    	usb_msc_create_disk (dev);
    } else if (prev_ready && !msc->ready) {
-		usb_debug ("usb msc: ready -> not ready (lun %d)\n", msc->lun);
+		usb_debug ("USB msc: ready -> not ready (lun %d)\n", msc->lun);
    	usb_msc_remove_disk (dev);
    } else if (!prev_ready && !msc->ready) {
    	u8 new_lun = (msc->lun + 1) % msc->num_luns;
-		usb_debug("usb msc: not ready (lun %d) -> lun %d\n", msc->lun,
+		usb_debug("USB msc: not ready (lun %d) -> lun %d\n", msc->lun,
    		  new_lun);
    	msc->lun = new_lun;
    }
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
index 4b6a250..f8e58fe 100644
--- a/payloads/libpayload/include/libpayload.h
+++ b/payloads/libpayload/include/libpayload.h
@@ -158,7 +158,7 @@
 /** @} */
/**
- * @defgroup usb USB functions
+ * @defgroup USB USB functions
  * @{
  */
 int usb_initialize(void);
diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h
index 8505c4f..5d27f7c 100644
--- a/payloads/libpayload/include/usb/usb.h
+++ b/payloads/libpayload/include/usb/usb.h
@@ -217,7 +217,7 @@
    hci_t *controller;
    endpoint_t endpoints[32];
    int num_endp;
-	int address;		// usb address
+	int address;		// USB address
    int hub;		// hub, device is attached to
    int port;		// port where device is attached
    usb_speed speed;
@@ -263,7 +263,7 @@
    u8* (*poll_intr_queue) (void *queue);
    void *instance;
-	/* set_address():		Tell the usb device its address (xHCI
+	/* set_address():		Tell the USB device its address (xHCI
    				controllers want to do this by
    				themselves). Also, allocate the usbdev
    				structure, initialize enpoint 0
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 5a3f2a6..97b39f4 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -382,7 +382,7 @@
    u32 portsc;
    int loop;
-	/* Reset the usb debug port */
+	/* Reset the USB debug port */
    portsc = read32(&ehci_regs->port_status[port - 1]);
    portsc &= ~PORT_PE;
    portsc |= PORT_RESET;
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index 13819f1..35f75c4 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -67,7 +67,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */
    { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */
    { 1, 0, -1 }, /* P2: Camera (no OC) */
@@ -120,7 +120,7 @@
    	.dimm_channel1_disabled = 2,
    	.max_ddr3_freq = 1600,
    	.usb_port_config = {
-			/* enabled   usb oc pin    length */
+			/* enabled   USB oc pin    length */
    		{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
    		{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
    		{ 1, 0, 0x0040 }, /* P2: Camera (no OC) */
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index c234e5b..7d1c177 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -154,7 +154,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 0, 0, -1 }, /* P0: Empty */
    { 1, 0, 0 }, /* P1: Left USB 1  (OC0) */
    { 1, 0, 1 }, /* P2: Left USB 2  (OC1) */
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c
index e36a1c7..4a109f1 100644
--- a/src/mainboard/google/mistral/mainboard.c
+++ b/src/mainboard/google/mistral/mainboard.c
@@ -26,7 +26,7 @@
static void setup_usb(void)
 {
-	/* Setting Secondary usb controller */
+	/* Setting Secondary USB controller */
    setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data);
 }
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 421826c..864837b 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -145,7 +145,7 @@
static void configure_usb_hub(void)
 {
-	/* set usb hub reset pin (low active) to high */
+	/* set USB hub reset pin (low active) to high */
    if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
    	gpio_output(GPIO(UTXD3), 1);
 }
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index 01c4526..917d165 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -116,7 +116,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 0, 0, -1 }, /* P0: Empty */
    { 1, 0, 0 }, /* P1: Left USB 1  (OC0) */
    { 1, 0, 1 }, /* P2: Left USB 2  (OC1) */
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index 07c19c5..b4e96f0 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -131,7 +131,7 @@
    	.dimm_channel1_disabled = 2,
    	.max_ddr3_freq = 1600,
    	.usb_port_config = {
-			/* enabled   usb oc pin    length */
+			/* enabled   USB oc pin    length */
    		{ 1, 0, 0x0040 }, /* P0: USB 3.0 1  (OC0) */
    		{ 1, 0, 0x0040 }, /* P1: USB 3.0 2  (OC0) */
    		{ 0, 1, 0x0000 }, /* P2: Empty */
@@ -171,7 +171,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled   usb oc pin    length */
+	/* enabled   USB oc pin    length */
    {1, 0, 0},  /* P0: USB 3.0 1  (OC0) */
    {1, 0, 0},  /* P1: USB 3.0 2  (OC0) */
    {0, 0, 0},  /* P2: Empty */
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 2d97c85..0bc5884 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -111,7 +111,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 1, 0, 0 }, /* P0: Front port  (OC0) */
    { 1, 0, 1 }, /* P1: Back port   (OC1) */
    { 1, 0, -1 }, /* P2: MINIPCIE1   (no OC) */
diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h
index ce059fd..c59cfd0 100644
--- a/src/mainboard/intel/harcuvar/hsio.h
+++ b/src/mainboard/intel/harcuvar/hsio.h
@@ -38,7 +38,7 @@
     *    Lane[19]->USB3 rear I/O panel connector
     */
-	/* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */
+	/* SKU HSIO 20 (pcie [0-15] sata [16-18] USB [19]) */
    {BL_SKU_HSIO_20,
    {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4},
    {/* ME_FIA_MUX_CONFIG */
@@ -155,7 +155,7 @@
    	   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	   BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */
+	/* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] USB [19]) */
    {BL_SKU_HSIO_12,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/*ME_FIA_MUX_CONFIG */
@@ -272,7 +272,7 @@
    	   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	   BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */
+	/* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] USB [19]) */
    {BL_SKU_HSIO_10,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
@@ -388,7 +388,7 @@
    	   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	   BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */
+	/* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] USB [19]) */
    {BL_SKU_HSIO_08,
    {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
@@ -504,7 +504,7 @@
    	   BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	   BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */
+	/* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] USB [19]) */
    {BL_SKU_HSIO_06,
    {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c
index eac19f4..df5f57e 100644
--- a/src/mainboard/kontron/ktqm77/early_init.c
+++ b/src/mainboard/kontron/ktqm77/early_init.c
@@ -99,7 +99,7 @@
    	.dimm_channel1_disabled = 2,
    	.max_ddr3_freq = 1600,
    	.usb_port_config = {
-			 /* enabled   usb oc pin    length */
+			 /* enabled   USB oc pin    length */
    		{ 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */
    		{ 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */
    		{ 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */
@@ -127,7 +127,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
    { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
    { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
index 04ddbe07..608ff2c 100644
--- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
@@ -27,7 +27,7 @@
    { 1, 0, 0 },  /* SSP1: right */
    { 1, 0, 1 },  /* SSP2: left, EHCI Debug */
    { 1, 1, 3 },  /* SSP3: dock usb3 */
-	{ 1, 1, -1 }, /* B0P4: wwan usb */
+	{ 1, 1, -1 }, /* B0P4: wwan USB */
    { 1, 1, 2 },  /* B0P5: dock usb2 */
    { 0, 0, -1 }, /* B0P6 */
    { 0, 0, -1 }, /* B0P7 */
@@ -36,7 +36,7 @@
    { 0, 2, 5 },  /* B1P2 */
    { 1, 1, -1 }, /* B1P3: fingerprint reader */
    { 0, 0, -1 }, /* B1P4 */
-	{ 1, 1, -1 }, /* B1P5: wlan usb */
+	{ 1, 1, -1 }, /* B1P5: wlan USB */
    { 1, 1, -1 }, /* B1P6: Camera */
 };
diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c
index 3380253..0249c3b 100644
--- a/src/mainboard/samsung/lumpy/early_init.c
+++ b/src/mainboard/samsung/lumpy/early_init.c
@@ -178,7 +178,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 1, 1, 0 }, /* P0: Port 0      (OC0) */
    { 1, 1, 1 }, /* P1: Port 1      (OC1) */
    { 1, 0, -1 }, /* P2: MINIPCIE1   (no OC) */
diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c
index d7f9b90..13da85a 100644
--- a/src/mainboard/samsung/stumpy/early_init.c
+++ b/src/mainboard/samsung/stumpy/early_init.c
@@ -167,7 +167,7 @@
 }
const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  usb oc pin  */
+	/* enabled power  USB oc pin  */
    { 1, 1, 0 }, /* P0: Front port  (OC0) */
    { 1, 0, 1 }, /* P1: Back port   (OC1) */
    { 1, 0, -1 }, /* P2: MINIPCIE1   (no OC) */
diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h
index e49fefd..aa6af53 100644
--- a/src/mainboard/scaleway/tagada/hsio.h
+++ b/src/mainboard/scaleway/tagada/hsio.h
@@ -38,7 +38,7 @@
     *    Lane[19]->USB3 rear I/O panel connector
     */
-	/* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+	/* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] USB [19]) */
    {BL_SKU_HSIO_20,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
@@ -155,7 +155,7 @@
    	    BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	    BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+	/* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] USB [19]) */
    {BL_SKU_HSIO_12,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
@@ -273,7 +273,7 @@
    	    BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	    BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+	/* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] USB [19]) */
    {BL_SKU_HSIO_10,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
@@ -391,7 +391,7 @@
    	    BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	    BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */
+	/* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] USB [19]) */
    {BL_SKU_HSIO_08,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
@@ -509,7 +509,7 @@
    	    BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
    	    BL_FIA_PCIE_ROOT_PORT_7)} } },
-	/* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */
+	/* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] USB []) */
    {BL_SKU_HSIO_06,
    {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
    {/* ME_FIA_MUX_CONFIG */
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index b9c5a4f..03e6dbd 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -842,7 +842,7 @@
/*
    	 * Override GLK xhci clock gating register(XHCLKGTEN) to
-		 * mitigate usb device suspend and resume failure.
+		 * mitigate USB device suspend and resume failure.
    	 */
    	if (CONFIG(SOC_INTEL_GLK)) {
    		uint32_t *cfg;
diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c
index 0fd41bf..d8ee29c 100644
--- a/src/soc/intel/common/block/xhci/elog.c
+++ b/src/soc/intel/common/block/xhci/elog.c
@@ -84,7 +84,7 @@
    	/*
    	 * Check if CSC bit is set and port is capable of wake on
    	 * connect/disconnect to identify if the port caused wake
-		 * event for usb attach/detach.
+		 * event for USB attach/detach.
    	 */
    	if (pch_xhci_csc_set(port_status) &&
    	    pch_xhci_wake_capable(port_status)) {
@@ -95,7 +95,7 @@
/*
    	 * Check if PLC is set and PLS indicates resume to identify if
-		 * the port caused wake event for usb activity.
+		 * the port caused wake event for USB activity.
    	 */
    	if (pch_xhci_plc_set(port_status) &&
    	    pch_xhci_resume(port_status)) {
diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c
index d80cfe9..b148093 100644
--- a/src/soc/mediatek/common/usb.c
+++ b/src/soc/mediatek/common/usb.c
@@ -104,7 +104,7 @@
do {
    	if (stopwatch_expired(&sw)) {
-			u3p_err("usb clocks are not stable!!!\n");
+			u3p_err("USB clocks are not stable!!!\n");
    		return -1;
    	}
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index d6003be..21c578f 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -214,7 +214,7 @@
 };
/*
- * The pci id of usb ctrl 0 and 1 are the same.
+ * The pci id of USB ctrl 0 and 1 are the same.
  */
 static const struct pci_driver usb_ohci123_driver __pci_driver = {
    .ops = &usb_ops,
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index a627cc1..fa578f7 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -99,7 +99,7 @@
    reg8 &= ~RTC_BATTERY_DEAD;
    pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-	/* usb transient disconnect */
+	/* USB transient disconnect */
    reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
    reg8 |= (3 << 0);
    pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
diff --git a/util/uio_usbdebug/uio_usbdebug_intel.c b/util/uio_usbdebug/uio_usbdebug_intel.c
index 9271896..2295cab 100644
--- a/util/uio_usbdebug/uio_usbdebug_intel.c
+++ b/util/uio_usbdebug/uio_usbdebug_intel.c
@@ -52,7 +52,7 @@
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 {
-	/* claim usb debug port */
+	/* claim USB debug port */
    const unsigned long dbgctl_addr =
    	((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET;
    write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30));
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Gerrit-Change-Number: 39100
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr
Gerrit-MessageType: newchange



    