Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However currently we do not configure/enable SuperIO chip. As result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c 3 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39782/1
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 8015f35..a24de71 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -21,6 +21,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SKYLAKE_SP + select SUPERIO_ASPEED_AST2400
config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 7a0a43f..27370fd 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ##
+bootblock-y += bootblock.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..c5329b1 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void enable_espi_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + + /* + * lpc_io_setup_comm_a_b() doesn't work, possibly because we use eSPI mode of the + * LPC/eSPI bridge. + */ + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch(com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/1/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/1/src/mainboard/ocp/tiogapass... PS1, Line 53: switch(com) { space required before the open parenthesis '('
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39782
to look at the new patch set (#2).
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However currently we do not configure/enable SuperIO chip. As result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c 3 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39782/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/2/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/2/src/mainboard/ocp/tiogapass... PS2, Line 42: switch(com) { space required before the open parenthesis '('
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 2: Code-Review+2
Works for me (on Tioga Pass)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/3/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/3/src/mainboard/ocp/tiogapass... PS3, Line 42: switch(com) { space required before the open parenthesis '('
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/39782/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39782/3//COMMIT_MSG@10 PS3, Line 10: currently we I'd use "we currently"
https://review.coreboot.org/c/coreboot/+/39782/3//COMMIT_MSG@10 PS3, Line 10: As result As *a* result
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, David Hendricks, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39782
to look at the new patch set (#4).
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c 3 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39782/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/4/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/4/src/mainboard/ocp/tiogapass... PS4, Line 42: switch(com) { space required before the open parenthesis '('
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 4:
(2 comments)
thanks. I wish a was a native speaker 😊
https://review.coreboot.org/c/coreboot/+/39782/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39782/3//COMMIT_MSG@10 PS3, Line 10: currently we
I'd use "we currently"
Done
https://review.coreboot.org/c/coreboot/+/39782/3//COMMIT_MSG@10 PS3, Line 10: As result
As *a* result
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 4: Code-Review+1
Patch Set 4:
(2 comments)
thanks. I wish a was a native speaker 😊
I'm not a native speaker myself 😄
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/5/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/5/src/mainboard/ocp/tiogapass... PS5, Line 42: switch(com) { space required before the open parenthesis '('
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, David Hendricks, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39782
to look at the new patch set (#6).
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c 3 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39782/6
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/6/src/mainboard/ocp/tiogapass... PS6, Line 17: espi espi or lpc?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, David Hendricks, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39782
to look at the new patch set (#7).
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c 3 files changed, 61 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39782/7
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39782/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39782/6/src/mainboard/ocp/tiogapass... PS6, Line 17: espi
espi or lpc?
it is LPC on TP but this bit is transparent to fw. I fixed the name
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
Patch Set 7: Code-Review+2
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39782 )
Change subject: mb/ocp/tiogapass: Properly configure early serial output ......................................................................
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov anpetrov@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c 3 files changed, 61 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 1d501e6..f9b5e7f 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_USES_FSP2_0 select IPMI_KCS select SOC_INTEL_SKYLAKE_SP + select SUPERIO_ASPEED_AST2400
config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 7a0a43f..27370fd 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ##
+bootblock-y += bootblock.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..d9a86e9 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +}
-
Andrey Petrov (Code Review) -
Angel Pons (Code Review)
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build bot (Jenkins) (Code Review)
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David Hendricks (Code Review)
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Maxim Polyakov (Code Review)