Rizwan Qureshi (rizwan.qureshi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18389
-gerrit
commit f299f8066fe6d6cc03aa9977b74919f2322431cc Author: Rizwan Qureshi rizwan.qureshi@intel.com Date: Fri Feb 17 19:36:23 2017 +0530
google/poppy: fix finger print sensor interrupt gpio configuration
Cofigure the right GPIOs for finger print sensor interrupt and reset lines.
Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- src/mainboard/google/poppy/gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index b3849f1..b02e976 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -100,8 +100,8 @@ static const struct pad_config gpio_table[] = { /* SML0ALERT# */ PAD_CFG_NC(GPP_C5), /* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */ +/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */ /* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11), /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ @@ -135,8 +135,8 @@ static const struct pad_config gpio_table[] = { /* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ /* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */ -/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */ /* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */ @@ -167,7 +167,7 @@ static const struct pad_config gpio_table[] = { NF1), /* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ +/* DDPD_HPD2 */ PAD_CFG_GPO(GPP_E15, 0, DEEP), /* TP48 */ /* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),