ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31042
Change subject: riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV ......................................................................
riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV
ARCH_RISCV_RV{32,64} will now select ARCH_RISCV.
Change-Id: Ia7a1a8f0bfab20e91b8429dd6dd3e9a4180a0a5b Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- M src/arch/riscv/Kconfig M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 3 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31042/1
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 5bde804..9d325af 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -40,10 +40,12 @@ config ARCH_RISCV_RV64 bool default n + select ARCH_RISCV
config ARCH_RISCV_RV32 bool default n + select ARCH_RISCV
config ARCH_RISCV_PMP bool @@ -52,7 +54,6 @@ config ARCH_BOOTBLOCK_RISCV bool default n - select ARCH_RISCV select C_ENVIRONMENT_BOOTBLOCK
config ARCH_VERSTAGE_RISCV diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 7910b37..6ebde33 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -13,7 +13,6 @@
config SOC_SIFIVE_FU540 bool - select ARCH_RISCV select ARCH_RISCV_RV64 select ARCH_RISCV_S select ARCH_RISCV_U diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index 5a43aa6..aa352d9 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,5 +1,4 @@ config SOC_UCB_RISCV - select ARCH_RISCV select ARCH_RISCV_RV64 select ARCH_RISCV_S select ARCH_RISCV_U
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31042 )
Change subject: riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV ......................................................................
Patch Set 1: Code-Review+2
It would be better to set this per stage. But this can be done in a separate change