[M] Change in coreboot[master]: soc/amd/picasso/acpi: factor out get_cstate_info functionality

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73425 )

Change subject: soc/amd/picasso/acpi: factor out get_cstate_info functionality
......................................................................

soc/amd/picasso/acpi: factor out get_cstate_info functionality

To be able to move generate_cpu_entries to the common AMD SoC code, the
SoC-specific C-state info needs to be factored out into a separate
get_cstate_info function that will remain in the SoC code.

Signed-off-by: Felix Held 
Change-Id: I8200bb9a0ccacd3c1020cee58f866d2f11671070
---
M src/soc/amd/picasso/acpi.c
1 file changed, 59 insertions(+), 37 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/73425/1

diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index c876f6c..dc714a9 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -230,15 +230,55 @@
    return pstate_count;
 }

+static const acpi_cstate_t cstate_info[] = {
+	[0] = {
+		.ctype = 1,
+		.latency = 1,
+		.power = 0,
+		.resource = {
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = 2,
+			.bit_offset = 2,
+			.addrl = 0,
+			.addrh = 0,
+		},
+	},
+	[1] = {
+		.ctype = 2,
+		.latency = 400,
+		.power = 0,
+		.resource = {
+			.space_id = ACPI_ADDRESS_SPACE_IO,
+			.bit_width = 8,
+			.bit_offset = 0,
+			.addrl = ACPI_CPU_CONTROL + 1,
+			.addrh = 0,
+			.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
+		},
+	},
+};
+
+static const acpi_cstate_t *get_cstate_info(size_t *cstate_count)
+{
+	uint32_t cstate_base_address =
+		rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;
+
+	if (cstate_base_address != ACPI_CPU_CONTROL) {
+		printk(BIOS_ERR, "C state IO port mismatch. Expected %x instead of %x.\n",
+		       ACPI_CPU_CONTROL, cstate_base_address);
+	}
+
+	*cstate_count = ARRAY_SIZE(cstate_info);
+	return cstate_info;
+}
+
 void generate_cpu_entries(const struct device *device)
 {
    int logical_cores;
-	size_t pstate_count, cpu;
+	size_t cstate_count, pstate_count, cpu;
    struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
    struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
    uint32_t threads_per_core;
-	uint32_t cstate_base_address =
-		rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;

const acpi_addr_t perf_ctrl = {
    	.space_id = ACPI_ADDRESS_SPACE_FIXED,
@@ -251,39 +291,7 @@
    	.addrl = PS_STS_REG,
    };

-	const acpi_cstate_t cstate_info[] = {
-		[0] = {
-			.ctype = 1,
-			.latency = 1,
-			.power = 0,
-			.resource = {
-				.space_id = ACPI_ADDRESS_SPACE_FIXED,
-				.bit_width = 2,
-				.bit_offset = 2,
-				.addrl = 0,
-				.addrh = 0,
-			},
-		},
-		[1] = {
-			.ctype = 2,
-			.latency = 400,
-			.power = 0,
-			.resource = {
-				.space_id = ACPI_ADDRESS_SPACE_IO,
-				.bit_width = 8,
-				.bit_offset = 0,
-				.addrl = ACPI_CPU_CONTROL + 1,
-				.addrh = 0,
-				.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
-			},
-		},
-	};
-
-	if (cstate_base_address != ACPI_CPU_CONTROL) {
-		printk(BIOS_ERR, "C state IO port mismatch. Expected %x, found %x.\n",
-		       ACPI_CPU_CONTROL, cstate_base_address);
-	}
-
+	const acpi_cstate_t *cstate_values = get_cstate_info(&cstate_count);
    threads_per_core = get_threads_per_core();
    pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
    logical_cores = get_cpu_count();
@@ -305,7 +313,7 @@

acpigen_write_PPC(0);

-		acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info));
+		acpigen_write_CST_package(cstate_values, cstate_count);

acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
    				  CSD_HW_ALL, 0);