[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email )

Change subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
......................................................................

drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug

Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the FSP heap is right above the
RC heap, where both of them are located at the bottom part of CAR.

Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.

TEST=intel/archercity CRB

Signed-off-by: Arthur Heymans 
Signed-off-by: Shuo Liu

Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: Shuo Liu 
---
M src/arch/x86/car.ld
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
5 files changed, 25 insertions(+), 2 deletions(-)

Approvals:
  Shuo Liu: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved
  Nico Huber: Looks good to me, approved

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 17e6eea..8e1af15 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -9,6 +9,10 @@
 .car.data . (NOLOAD) : {
    _car_region_start = . ;
    . += CONFIG_FSP_M_RC_HEAP_SIZE;
+#if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND)
+	REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16)
+#endif
+
 #if CONFIG(PAGING_IN_CACHE_AS_RAM)
    /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
     * aligned when using this option. */
@@ -107,7 +111,7 @@

. = _car_region_start;
 .car.fspm_rc_heap . (NOLOAD) : {
-. += CONFIG_FSP_M_RC_HEAP_SIZE;
+	. += CONFIG_FSP_M_RC_HEAP_SIZE;
 }

. = _car_region_end;
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index e27249f..274c3e5 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -221,6 +221,17 @@
      without reinitializing stack pointer. This feature is
      supported Icelake onwards.

+config FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
+	bool
+	help
+	 Starting with Intel CPX there is a bug in there reference code during
+	 the pipe init. This code synchronises the CAR between sockets in FSP-M.
+	 This code implicitly assumes that the FSP heap is right above the
+	 RC heap, where both of them are located at the bottom part of CAR.
+	 Select this to have an explicit handling of the FSP StackBase to work
+	 around this issue. This is needed on multi-socket Xeon-SP systems.
+	 This will place the FSP heap right above the FSP-M RC heap.
+
 config FSP_TEMP_RAM_SIZE
    hex
    help
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index f5de5c3..c096e86 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -170,7 +170,13 @@
    	[FSP_BOOT_IN_RECOVERY_MODE] = "boot in recovery mode",
    };

-	if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) {
+	if (CONFIG(FSP_USES_CB_STACK) && ENV_RAMINIT
+	    && CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND)) {
+		extern char _fspm_heap[];
+		extern char _efspm_heap[];
+		arch_upd->StackBase = (uintptr_t)_fspm_heap;
+		arch_upd->StackSize = (size_t)(_efspm_heap - _fspm_heap);
+	} else if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) {
    	arch_upd->StackBase = (uintptr_t)temp_ram;
    	arch_upd->StackSize = sizeof(temp_ram);
    } else if (setup_fsp_stack_frame(arch_upd, memmap)) {
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index ac166c3..b9d63d3 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -7,6 +7,7 @@
    select CACHE_MRC_SETTINGS
    select NO_FSP_TEMP_RAM_EXIT
    select HAVE_INTEL_FSP_REPO
+	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
    help
      Intel Cooper Lake-SP support

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index bb88bec..ace5c07 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -13,6 +13,7 @@
    select SOC_INTEL_CSE_SERVER_SKU
    select XEON_SP_COMMON_BASE
    select HAVE_IOAT_DOMAINS
+	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
    help
      Intel Sapphire Rapids-SP support