Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41807 )
Change subject: mb/google/dedede: Enable Heci1 device ......................................................................
mb/google/dedede: Enable Heci1 device
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow.
TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra aamir.bohra@intel.com
Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/41807/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e..6509f19 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -255,7 +255,7 @@ device pci 15.1 on end # I2C 1 device pci 15.2 on end # I2C 2 device pci 15.3 on end # I2C 3 - device pci 16.0 off end # HECI 1 + device pci 16.0 on end # HECI 1 device pci 16.1 off end # HECI 2 device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41807 )
Change subject: mb/google/dedede: Enable Heci1 device ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41807 )
Change subject: mb/google/dedede: Enable Heci1 device ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41807 )
Change subject: mb/google/dedede: Enable Heci1 device ......................................................................
mb/google/dedede: Enable Heci1 device
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow.
TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra aamir.bohra@intel.com
Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1b42dfb..fc43976 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -258,7 +258,7 @@ device pci 15.1 on end # I2C 1 device pci 15.2 on end # I2C 2 device pci 15.3 on end # I2C 3 - device pci 16.0 off end # HECI 1 + device pci 16.0 on end # HECI 1 device pci 16.1 off end # HECI 2 device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41807 )
Change subject: mb/google/dedede: Enable Heci1 device ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4438 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4437 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4436 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4435
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aamir Bohra (Code Review)
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Karthik Ramasubramanian (Code Review)
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Tim Wawrzynczak (Code Review)