Change in coreboot[master]: soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54391 )

Change subject: soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl
......................................................................

soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl

We were not adding power management handling of GPIO_COM3 in gpio.asl
This can affect s0ix flow where platform won't go into s0ix since
GPIO_COM3 is not power gated.

BUG=b:188392183
BRANCH=None
TEST=Platform should enter to s0ix and GPIO COMM3 should not block an
entry to s0ix.

Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/acpi/gpio.asl
1 file changed, 10 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl
index 50d999f..376afab 100644
--- a/src/soc/intel/alderlake/acpi/gpio.asl
+++ b/src/soc/intel/alderlake/acpi/gpio.asl
@@ -80,6 +80,12 @@
    	Local0 = PID_GPIOCOM2
    	Local1 = Arg0 - GPIO_COM2_START
    }
+	/* GPIO Community 3 */
+	If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END)
+	{
+		Local0 = PID_GPIOCOM3
+		Local1 = Arg0 - GPIO_COM3_START
+	}
    /* GPIO Community 4 */
    If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
    {
@@ -115,6 +121,9 @@
    	Case (COMM_2) {
    		Local0 = PID_GPIOCOM2
    	}
+		case (COMM_3) {
+			Local0 = PID_GPIOCOM3
+		}
    	Case (COMM_4) {
    		Local0 = PID_GPIOCOM4
    	}
@@ -130,7 +139,7 @@
 }

/* GPIO Power Management bits */
-Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0, 0})

/*
  * Save GPIO Power Management bits