[S] Change in coreboot[main]: mb/google/brox: Check to powergate the UFS controller

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Karthik Ramasubramanian.

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86151?usp=email

to look at the new patch set (#3).

Change subject: mb/google/brox: Check to powergate the UFS controller
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mb/google/brox: Check to powergate the UFS controller

On boards with non-UFS storage, during certain kind of resets UFS
controller is not powergated even though it is disabled. This leads to
suspend/resume failures during that boot cycle. UFS controller is always
disabled in romstage. If the UFS controller is disabled in devicetree
and is not powergated, then trigger an extra reset for UFS disablement
to take effect.

BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode.
[INFO ]  ISH Status: 0x7f, UFS0 Status: 0x60
[ERROR]  ISH and/or UFS not powergated.
[INFO ]  fw_config match found: RETIMER=RETIMER_JHL8040
[INFO ]  CBFS: Found 'rts5453_retimer_jhl8040.hash' @0x92740 size 0x3 in mcache @0x76abc410
[INFO ]  VB2:vb2_digest_init() 3 bytes, hash algo 2, HW acceleration enabled
[INFO ]  Triggering warm reset to disable UFS
[INFO ]  system_reset() called!

Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
R src/mainboard/google/brox/variants/baseboard/brox/reset_check.c
3 files changed, 47 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86151/3