Change in coreboot[master]: mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVP

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang.
Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63946 )

Change subject: mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVP
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Patch Set 5:

(1 comment)

File src/mainboard/intel/adlrvp/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/63946/comment/edabfdff_b4e77915 
PS5, Line 429: 		device ref pcie_rp3 on end # W/A to FSP issue
             : 		device ref pcie_rp4 on end # W/A to FSP issue
> the comment says WA for FSP issue. […]

This was ported to start with initially, probably ported from ADL-M RVP (src/mainboard/intel/adlrvp/devicetree_m.cb).  There is no specific changes just for these two lines. It also results in warning messages in PCIe clock assignment. I tested and I didn't run into any problem.