Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47336 )
Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ......................................................................
soc/intel/elkhartlake: Add Initial support for Intel PSE
Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization.
This patch add initial PSE loading support for EHL.
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I96e779021938689e0f9a96046b9c292f3ff1db4e --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47336/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 89da0be..7fc2e5f 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -194,6 +194,19 @@ config FSP_FD_PATH default "3rdparty/fsp/ElkhartLakeFspBinPkg/Fsp.fd"
+config PSE_IMAGE + bool "Add a PSE binary to CBFS" + help + Add a PSE binary file to CBFS. The PSE describes the integrated + programmable service engine that is designed as an Asymmetric + Multi-Processing (AMP) system. + +config PSE_IMAGE_FILE + string "PSE binary path and filename" + depends on PSE_IMAGE + help + The path and filename of the PSE binary. + config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT int "Debug Consent for EHL" # USB DBC is more common for developers so make this default to 3 if diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..9456d4e 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -57,4 +57,10 @@ CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake/include
+cbfs-files-$(CONFIG_PSE_IMAGE) += pse.bin +pse.bin-file := $(CONFIG_PSE_IMAGE_FILE) +pse.bin-type := raw +pse.bin-align := 0x1000 +pse.bin-compression := lzma + endif diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 3d740fb..4ec2cab 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -59,8 +59,14 @@ /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params);
- /* TODO: Update with UPD override as FSP matures */
+ if (CONFIG(PSE_IMAGE)){ + //uint32_t psebase =0x0; + static char psefw[256 * KiB]; + size_t psefwsize = cbfs_boot_load_file("pse.bin", + psefw, sizeof(psefw), CBFS_TYPE_RAW); + params->SiipRegionBase = (uint32_t)&psefw; + params->SiipRegionSize = psefwsize; /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47336 )
Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47336/1/src/soc/intel/elkhartlake/f... File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47336/1/src/soc/intel/elkhartlake/f... PS1, Line 63: if (CONFIG(PSE_IMAGE)){ suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47336/1/src/soc/intel/elkhartlake/f... PS1, Line 63: if (CONFIG(PSE_IMAGE)){ space required before the open brace '{'
Attention is currently required from: Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47336 )
Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47336/comment/dc255b85_19186317 PS1, Line 69: params->SiipRegionSize = psefwsize; Please clean up the code (missing closing curly, remove unused psebase, do not guard "mainboard_silicon_init_params(params);" with "if (CONFIG(PSE_IMAGE)){".
Attention is currently required from: Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47336 )
Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ......................................................................
Patch Set 1:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47336/comment/3ba5b94a_79b20bae PS1, Line 2: Tan, Lean Sheng Please use *Lean Sheng Tan*.
https://review.coreboot.org/c/coreboot/+/47336/comment/9fe9e422_b4483725 PS1, Line 11: low-DMIPS computing What does that mean?
https://review.coreboot.org/c/coreboot/+/47336/comment/3028c5d4_de2647a6 PS1, Line 15: add adds
https://review.coreboot.org/c/coreboot/+/47336/comment/5b8d3674_05a13ef7 PS1, Line 15: This patch add initial PSE loading support for EHL. Please describe the coreboot integration in detail. It looks like it’s implemented by loading a blob. What does the blob do? Where will the blob be published? Why is a blob needed at all?
https://review.coreboot.org/c/coreboot/+/47336/comment/1c57260d_243cb3fd PS1, Line 16: 1. Tested how? 2. Please add a reference to the specification.
File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47336/comment/d3fae5c3_59cfbda0 PS1, Line 200: PSE Please spell it out once in the help text.
Lean Sheng Tan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47336 )
Change subject: soc/intel/elkhartlake: Add Initial support for Intel PSE ......................................................................
Abandoned
Will resubmit a new one
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build bot (Jenkins) (Code Review) -
Lean Sheng Tan (Code Review)
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Paul Menzel (Code Review)
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Werner Zeh (Code Review)