Lean Sheng Tan has uploaded this change for review.
soc/intel/elkhartlake: Add Initial support for Intel PSE
Intel® Programmable Services Engine (Intel® PSE) is a dedicated
offload engine for IoT functions powered by an ARM Cortex-M7
microcontroller. It provides independent, low-DMIPS computing and
low-speed I/Os for IoT applications, plus dedicated services for
real-time computing and time-sensitive synchronization.
This patch add initial PSE loading support for EHL.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I96e779021938689e0f9a96046b9c292f3ff1db4e
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/Makefile.inc
M src/soc/intel/elkhartlake/fsp_params.c
3 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47336/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 89da0be..7fc2e5f 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -194,6 +194,19 @@
config FSP_FD_PATH
default "3rdparty/fsp/ElkhartLakeFspBinPkg/Fsp.fd"
+config PSE_IMAGE
+ bool "Add a PSE binary to CBFS"
+ help
+ Add a PSE binary file to CBFS. The PSE describes the integrated
+ programmable service engine that is designed as an Asymmetric
+ Multi-Processing (AMP) system.
+
+config PSE_IMAGE_FILE
+ string "PSE binary path and filename"
+ depends on PSE_IMAGE
+ help
+ The path and filename of the PSE binary.
+
config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT
int "Debug Consent for EHL"
# USB DBC is more common for developers so make this default to 3 if
diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc
index 5c46f86..9456d4e 100644
--- a/src/soc/intel/elkhartlake/Makefile.inc
+++ b/src/soc/intel/elkhartlake/Makefile.inc
@@ -57,4 +57,10 @@
CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake
CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake/include
+cbfs-files-$(CONFIG_PSE_IMAGE) += pse.bin
+pse.bin-file := $(CONFIG_PSE_IMAGE_FILE)
+pse.bin-type := raw
+pse.bin-align := 0x1000
+pse.bin-compression := lzma
+
endif
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 3d740fb..4ec2cab 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -59,8 +59,14 @@
/* Parse device tree and fill in FSP UPDs */
parse_devicetree(params);
- /* TODO: Update with UPD override as FSP matures */
+ if (CONFIG(PSE_IMAGE)){
+ //uint32_t psebase =0x0;
+ static char psefw[256 * KiB];
+ size_t psefwsize = cbfs_boot_load_file("pse.bin",
+ psefw, sizeof(psefw), CBFS_TYPE_RAW);
+ params->SiipRegionBase = (uint32_t)&psefw;
+ params->SiipRegionSize = psefwsize;
/* Override/Fill FSP Silicon Param for mainboard */
mainboard_silicon_init_params(params);
}
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