Change in coreboot[master]: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40809 )

Change subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
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sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/i82371eb/isa.c
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/40809/1

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index bb87611..f7c38fe 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -40,9 +40,7 @@
    /*
     * Enable special cycles, needed for soft poweroff.
     */
-	reg32 = pci_read_config16(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SPECIAL;
-	pci_write_config16(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);

/*
     * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40809 )

Change subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40809 )

Change subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
......................................................................

sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/i82371eb/isa.c
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index efbfb22..ae35d90 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -27,9 +27,7 @@
    /*
     * Enable special cycles, needed for soft poweroff.
     */
-	reg32 = pci_read_config16(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SPECIAL;
-	pci_write_config16(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);

/*
     * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40809 )

Change subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4624
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4623
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4622
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4621

Please note: This test is under development and might not be accurate at all!