Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46726 )
Change subject: sb/intel/lynxpoint: Align with Broadwell ......................................................................
sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 22 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46726/1
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index d142d3e..802c58e 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,9 +7,7 @@
static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index b61115b..24897ca 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -46,7 +46,7 @@ /* Write back the value once reset bit is set. */ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
- /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 8360ce6..7eef5ff 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,11 +289,14 @@
pci_write_config8(dev, 0xa9, 0x46);
- RCBA32_AND_OR(0x232c, ~1, 0x00000000); + RCBA32_AND_OR(0x232c, ~1, 0); + RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); RCBA32_OR(0x1100, 0x00000100); RCBA32_OR(0x1100, 0x0000003f); + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + RCBA32(0x3314) = 0x00012fff; RCBA32(0x3318) = 0x0dcf0400; RCBA32(0x3324) = 0x04000000; @@ -320,19 +323,24 @@ RCBA32(0x3a20) = 0x00000404; RCBA32(0x3a24) = 0x01010101; RCBA32(0x3a30) = 0x01010101; + RCBA32_OR(0x0410, 0x00000003); RCBA32_OR(0x2618, 0x08000000); RCBA32_OR(0x2300, 0x00000002); RCBA32_OR(0x2600, 0x00000008); + RCBA32(0x33b4) = 0x00007001; RCBA32(0x3350) = 0x022ddfff; RCBA32(0x3354) = 0x00000001; - RCBA32_OR(0x33d4, 0x08000000); /* Power Optimizer */ - RCBA32_OR(0x33c8, 0x00000080); /* Power Optimizer */ - RCBA32(0x2b10) = 0x0000883c; /* Power Optimizer */ - RCBA32(0x2b14) = 0x1e0a4616; /* Power Optimizer */ - RCBA32(0x2b24) = 0x40000005; /* Power Optimizer */ - RCBA32(0x2b20) = 0x0005db01; /* Power Optimizer */ + + /* Power Optimizer */ + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; RCBA32(0x3a80) = 0x05145005;
pci_or_config32(dev, 0xac, 1 << 21); @@ -432,7 +440,7 @@ * RCBA + 0x2614[30:28] = 0x0 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ - RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); + RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500);
/* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ struct device *const gma = pcidev_on_root(2, 0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8b791f7..9c68a54 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -144,12 +144,12 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; else reg8 |= 1; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -387,7 +387,7 @@
// BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL);
if (bios_cntl & 1) { /* @@ -401,7 +401,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46726
to look at the new patch set (#4).
Change subject: sb/intel/lynxpoint: Align with Broadwell ......................................................................
sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 22 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46726/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46726
to look at the new patch set (#6).
Change subject: sb/intel/lynxpoint: Align with Broadwell ......................................................................
sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 22 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46726/6
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46726 )
Change subject: sb/intel/lynxpoint: Align with Broadwell ......................................................................
Patch Set 11: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46726 )
Change subject: sb/intel/lynxpoint: Align with Broadwell ......................................................................
sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 22 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index d142d3e..802c58e 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,9 +7,7 @@
static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index b61115b..24897ca 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -46,7 +46,7 @@ /* Write back the value once reset bit is set. */ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
- /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 23066ebd..4286e6ca 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,11 +289,14 @@
pci_write_config8(dev, 0xa9, 0x46);
- RCBA32_AND_OR(0x232c, ~1, 0x00000000); + RCBA32_AND_OR(0x232c, ~1, 0); + RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); RCBA32_OR(0x1100, 0x00000100); RCBA32_OR(0x1100, 0x0000003f); + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + RCBA32(0x3314) = 0x00012fff; RCBA32(0x3318) = 0x0dcf0400; RCBA32(0x3324) = 0x04000000; @@ -320,19 +323,24 @@ RCBA32(0x3a20) = 0x00000404; RCBA32(0x3a24) = 0x01010101; RCBA32(0x3a30) = 0x01010101; + RCBA32_OR(0x0410, 0x00000003); RCBA32_OR(0x2618, 0x08000000); RCBA32_OR(0x2300, 0x00000002); RCBA32_OR(0x2600, 0x00000008); + RCBA32(0x33b4) = 0x00007001; RCBA32(0x3350) = 0x022ddfff; RCBA32(0x3354) = 0x00000001; - RCBA32_OR(0x33d4, 0x08000000); /* Power Optimizer */ - RCBA32_OR(0x33c8, 0x00000080); /* Power Optimizer */ - RCBA32(0x2b10) = 0x0000883c; /* Power Optimizer */ - RCBA32(0x2b14) = 0x1e0a4616; /* Power Optimizer */ - RCBA32(0x2b24) = 0x40000005; /* Power Optimizer */ - RCBA32(0x2b20) = 0x0005db01; /* Power Optimizer */ + + /* Power Optimizer */ + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; RCBA32(0x3a80) = 0x05145005;
pci_or_config32(dev, 0xac, 1 << 21); @@ -432,7 +440,7 @@ * RCBA + 0x2614[30:28] = 0x0 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ - RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); + RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500);
/* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ struct device *const gma = pcidev_on_root(2, 0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8b791f7..9c68a54 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -144,12 +144,12 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; else reg8 |= 1; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -387,7 +387,7 @@
// BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL);
if (bios_cntl & 1) { /* @@ -401,7 +401,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)