Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28791

Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
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soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers

This patch save and restore ITSS IPCx register before and after
FSP-S call.

Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/soc/itss.h
3 files changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/28791/1

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 9d9ca01..6a7cc17 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -21,19 +21,29 @@
 #include <device/pci.h>
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <soc/acpi.h>
 #include <soc/interrupt.h>
 #include <soc/irq.h>
+#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>

void soc_init_pre_device(void *chip_info)
 {
+	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
+	 * default policy that doesn't honor boards' requirements. */
+	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
    /* Perform silicon specific init. */
    intel_silicon_init();
+
+	/* Restore GPIO IRQ polarities back to previous settings. */
+	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
 }

void soc_fsp_load(void)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index c2c0745..980b7e6 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -30,6 +30,7 @@
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
@@ -38,6 +39,7 @@
 #include <soc/interrupt.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
+#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
@@ -168,8 +170,16 @@

void soc_init_pre_device(void *chip_info)
 {
+	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
+	 * default policy that doesn't honor boards' requirements. */
+	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
    /* Perform silicon specific init. */
    fsp_silicon_init(romstage_handoff_is_resume());
+
+	/* Restore GPIO IRQ polarities back to previous settings. */
+	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
    /* swap enabled PCI ports in device tree if needed */
    pcie_override_devicetree_after_silicon_init();
 }
diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h
index 5ff9bb1..e6eb8b0 100644
--- a/src/soc/intel/skylake/include/soc/itss.h
+++ b/src/soc/intel/skylake/include/soc/itss.h
@@ -16,6 +16,9 @@
 #ifndef SOC_INTEL_SKL_ITSS_H
 #define SOC_INTEL_SKL_ITSS_H

+#define GPIO_IRQ_START	50
+#define GPIO_IRQ_END	ITSS_MAX_IRQ
+
 #define ITSS_MAX_IRQ	119
 #define IRQS_PER_IPC	32
 #define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)