Change in coreboot[master]: mb/google/brya/var/crota: setting for codec reset pin

[Terry Chen (Code Review)]

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64027 )

Change subject: mb/google/brya/var/crota: setting for codec reset pin
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mb/google/brya/var/crota: setting for codec reset pin

The audio codec of Crota360 used is Cirrus CS42L42, different from Brya (Realtek ALC5682I)
There is no Reset pin on ALC5682 but CS42L42 is needed.
So we use GPP_B15 for the reset pin of CS42L42 controlled that make the power sequence well.

BUG=b:230074351
BRANCH=none
TEST=build coreboot without error

Signed-off-by: Terry Chen 
Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14
---
M src/mainboard/google/brya/variants/crota/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/64027/1

diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c
index ee8ee19..881f78d 100644
--- a/src/mainboard/google/brya/variants/crota/gpio.c
+++ b/src/mainboard/google/brya/variants/crota/gpio.c
@@ -22,8 +22,8 @@
    PAD_NC(GPP_B2, NONE),
    /* B3  : PROC_GP2 ==> NC */
    PAD_NC(GPP_B3, NONE),
-	/* B15 : TIME_SYNC0 ==> NC */
-	PAD_NC(GPP_B15, NONE),
+	/* B15  : PROC_GP3 ==> AUD_RST_L */
+	PAD_CFG_GPO(GPP_B15, 1, PWROK),

/* C3  : GPP_C3 ==> SML0_SMBCLK */
    PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),