[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable

[Jonathon Hall (Code Review)]

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Reagan, Sean Rhodes, Tim Crawford.

Jonathon Hall has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )

Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
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Patch Set 2:

(2 comments)

File src/mainboard/purism/librem_skl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/79917/comment/6cb388e0_9e4214eb?usp... :
PS2, Line 141: 	register "PcieRpEnable[4]" = "1"
> Tested librem_13v2.  The device tree should have pcie_rp5, not pcie_rp1. […]

I fixed librem_skl in CB:80065.

File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/79917/comment/d4055f97_8a488bf5?usp... :
PS2, Line 190: 		device ref pcie_rp1	on  end
> I happen to have a very similar board (see CB:82506). You are indeed correct. […]

IIRC, it's because a PCI device has to have a function 0 so it can be enumerated.  If the root port corresponding to function 0 isn't enabled, the PCH promotes the first enabled function to function 0.