Change in coreboot[master]: stoneyridge: Enable spread spectrum in bootblock

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27813

Change subject: stoneyridge: Enable spread spectrum in bootblock
......................................................................

stoneyridge: Enable spread spectrum in bootblock

setup_spread_spectrum is called in early_init, meaning the console is
not initialized yet. So you won't see boot block booting twice.

BUG=b:111610455
TEST=booted grunt and verified that AmdInitReset does not reboot. I had
AGESA patched to skip the JTAG check.

Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6
Signed-off-by: Raul E Rangel 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/sb_util.c
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 89 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27813/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 15c9581..64b4b46 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -367,6 +367,28 @@
 #define GPP_CLK0_CLOCK_REQ_MAP_MASK	(0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
 #define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0	1

+/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */
+#define MISC_CGPLL_CONFIG1			0x08
+#define   CG1PLL_SPREAD_SPECTRUM_ENABLE		BIT(0)
+#define MISC_CGPLL_CONFIG3			0x10
+#define   CG1PLL_REFDIV_SHIFT			0
+#define   CG1PLL_REFDIV_MASK			(0x3FF << CG1PLL_REFDIV_SHIFT)
+#define   CG1PLL_FBDIV_SHIFT			10
+#define   CG1PLL_FBDIV_MASK			(0xFFF << CG1PLL_FBDIV_SHIFT)
+#define MISC_CGPLL_CONFIG4			0x14
+#define   CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT	0
+#define   CG1PLL_SS_STEP_SIZE_DSFRAC_MASK	(0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
+#define   CG1PLL_SS_AMOUNT_DSFRAC_SHIFT		16
+#define   CG1PLL_SS_AMOUNT_DSFRAC_MASK		(0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
+#define MISC_CGPLL_CONFIG5			0x18
+#define   CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT	8
+#define   CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK	(0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
+#define MISC_CGPLL_CONFIG6			0x1C
+#define   CG1PLL_LF_MODE_SHIFT			9
+#define   CG1PLL_LF_MODE_MASK			(0x1FF << CG1PLL_LF_MODE_SHIFT)
+#define MISC_CLK_CNTL1				0x40
+#define   CG1PLL_FBDIV_TEST			BIT(26)
+
 struct stoneyridge_aoac {
    int enable;
    int status;
@@ -404,6 +426,8 @@
 void pm_write8(u8 reg, u8 value);
 void pm_write16(u8 reg, u16 value);
 void pm_write32(u8 reg, u32 value);
+u32 misc_read32(u8 reg);
+void misc_write32(u8 reg, u32 value);
 uint8_t smi_read8(uint8_t offset);
 uint16_t smi_read16(uint8_t offset);
 uint32_t smi_read32(uint8_t offset);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 26c86e8..9daf0bb 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -36,6 +36,16 @@
    return read16((void *)(PM_MMIO_BASE + reg));
 }

+void misc_write32(u8 reg, u32 value)
+{
+	write32((void *)(MISC_MMIO_BASE + reg), value);
+}
+
+u32 misc_read32(u8 reg)
+{
+	return read32((void *)(MISC_MMIO_BASE + reg));
+}
+
 void pm_write32(u8 reg, u32 value)
 {
    write32((void *)(PM_MMIO_BASE + reg), value);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 63d8806..0040de3 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -33,6 +33,7 @@
 #include <soc/pci_devs.h>
 #include <agesa_headers.h>
 #include <soc/nvs.h>
+#include <reset.h>

/*
  * Table of devices that need their AOAC registers enabled and waited
@@ -541,6 +542,59 @@
    }
 }

+static void setup_spread_spectrum(void)
+{
+	uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
+
+	rstcfg &= ~TOGGLE_ALL_PWR_GOOD;
+	pm_write16(PWR_RESET_CFG, rstcfg);
+
+	uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);
+
+	if (cntl1 & CG1PLL_FBDIV_TEST) {
+		printk(BIOS_DEBUG, "Spread spectrum is ready\n");
+		misc_write32(MISC_CGPLL_CONFIG1,
+			     misc_read32(MISC_CGPLL_CONFIG1) |
+				     CG1PLL_SPREAD_SPECTRUM_ENABLE);
+
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Setting up spread spectrum\n");
+
+	uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
+	cfg6 &= ~CG1PLL_LF_MODE_MASK;
+	cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
+	misc_write32(MISC_CGPLL_CONFIG6, cfg6);
+
+	uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
+	cfg3 &= ~CG1PLL_REFDIV_MASK;
+	cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
+	cfg3 &= ~CG1PLL_FBDIV_MASK;
+	cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
+	misc_write32(MISC_CGPLL_CONFIG3, cfg3);
+
+	uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
+	cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK;
+	cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK;
+	misc_write32(MISC_CGPLL_CONFIG5, cfg5);
+
+	uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
+	cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK;
+	cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;
+	cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;
+	cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;
+	misc_write32(MISC_CGPLL_CONFIG4, cfg4);
+
+	rstcfg |= TOGGLE_ALL_PWR_GOOD;
+	pm_write16(PWR_RESET_CFG, rstcfg);
+
+	cntl1 |= CG1PLL_FBDIV_TEST;
+	misc_write32(MISC_CLK_CNTL1, cntl1);
+
+	soft_reset();
+}
+
 void bootblock_fch_early_init(void)
 {
    sb_enable_rom();
@@ -553,6 +607,7 @@
    sb_enable_cf9_io();
    sb_enable_legacy_io();
    enable_aoac_devices();
+	setup_spread_spectrum();
 }

void sb_enable(device_t dev)