Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39626
to review the following change.
Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ......................................................................
soc/mediatek/mt8183: Fix wrong setting of DRS config
Update setting of DRS config
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c 1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39626/1
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index dc3676a..67ed2db 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -486,9 +486,10 @@
/* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), - (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) | + (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21), + (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) | + (0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset();
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39626 )
Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39626/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39626/1//COMMIT_MSG@9 PS1, Line 9: g Please add a trailing ".".
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39626 )
Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ......................................................................
Patch Set 1: Code-Review+2
It would be even better if you can explain what was wrong in the description, especially there is no bugs associated.
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Yu-Ping Wu, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39626
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ......................................................................
soc/mediatek/mt8183: Fix wrong setting of DRS config
Update setting of DRS config.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c 1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39626/2
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39626 )
Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39626/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39626/1//COMMIT_MSG@9 PS1, Line 9: g
Please add a trailing ".".
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39626 )
Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ......................................................................
soc/mediatek/mt8183: Fix wrong setting of DRS config
Update setting of DRS config.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan huayang.duan@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39626 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c 1 file changed, 4 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 0ee4794..850f2b2 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -485,9 +485,10 @@
/* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), - (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) | + (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21), + (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) | + (0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset();
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Duan huayang (Code Review) -
huayang duan (Code Review)
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Hung-Te Lin (Code Review)
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Patrick Georgi (Code Review)
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Yu-Ping Wu (Code Review)