Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38027 )
Change subject: nb/intel/sandybridge: replace .val_4028 with .io_latency ......................................................................
nb/intel/sandybridge: replace .val_4028 with .io_latency
Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38027/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3cc9d29..7da5ad6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1026,7 +1026,7 @@ shift_402x = -1;
reg_io_latency |= - (ctrl->timings[channel][slotrank].val_4028 + shift_402x - + (ctrl->timings[channel][slotrank].io_latency + shift_402x - post_timA_min_high) << (4 * slotrank); reg_4024 |= (ctrl->timings[channel][slotrank].val_4024 + @@ -1260,9 +1260,9 @@ printram("4024 -= 2;\n"); continue; } - ctrl->timings[channel][slotrank].val_4028 += 2; + ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { + if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); return MAKE_ERR; @@ -1321,7 +1321,7 @@ else shift_402x = 0;
- ctrl->timings[channel][slotrank].val_4028 += shift_402x; + ctrl->timings[channel][slotrank].io_latency += shift_402x; ctrl->timings[channel][slotrank].val_4024 += shift_402x; printram("4024 += %d;\n", shift_402x); printram("4028 += %d;\n", shift_402x); @@ -1367,7 +1367,7 @@
MCHBAR32(0x3400) = (slotrank << 2) | 0x8001;
- ctrl->timings[channel][slotrank].val_4028 = 4; + ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].val_4024 = 55; program_timings(ctrl, channel);
@@ -1384,7 +1384,7 @@ }
if (all_high) { - ctrl->timings[channel][slotrank].val_4028--; + ctrl->timings[channel][slotrank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -1394,7 +1394,7 @@ } } else if (some_high) { ctrl->timings[channel][slotrank].val_4024++; - ctrl->timings[channel][slotrank].val_4028++; + ctrl->timings[channel][slotrank].io_latency++; printram("4024++;\n"); printram("4028++;\n"); } @@ -1418,14 +1418,14 @@ FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; } - ctrl->timings[channel][slotrank].val_4028 -= mnmx.timA_min_high; + ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; printram("4028 -= %d;\n", mnmx.timA_min_high);
post_timA_change(ctrl, channel, slotrank, &mnmx);
printram("4/8: %d, %d, %x, %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_4024, - ctrl->timings[channel][slotrank].val_4028); + ctrl->timings[channel][slotrank].io_latency);
printram("final results:\n"); FOR_ALL_LANES @@ -1913,7 +1913,7 @@ MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + - ctrl->timings[channel][slotrank].val_4028) << 16); + ctrl->timings[channel][slotrank].io_latency) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; MCHBAR32(0x4218 + 0x400 * channel) = 0;
@@ -2931,12 +2931,12 @@ printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat);
- delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; + delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; printram("normalize %d, %d, %d: delta %d\n", channel, slotrank, lane, delta);
ctrl->timings[channel][slotrank].val_4024 += delta; - ctrl->timings[channel][slotrank].val_4028 += delta; + ctrl->timings[channel][slotrank].io_latency += delta; }
FOR_ALL_POPULATED_CHANNELS { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 6bbc8b3..d11c044 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -54,8 +54,8 @@ struct ram_rank_timings { /* Register 4024. One byte per slotrank. */ u8 val_4024; - /* Register 4028. One nibble per slotrank. */ - u8 val_4028; + /* IO_LATENCY register. One nibble per slotrank. */ + u8 io_latency;
int val_320c;
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38027 )
Change subject: nb/intel/sandybridge: replace .val_4028 with .io_latency ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38027 )
Change subject: nb/intel/sandybridge: replace .val_4028 with .io_latency ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38027 )
Change subject: nb/intel/sandybridge: replace .val_4028 with .io_latency ......................................................................
nb/intel/sandybridge: replace .val_4028 with .io_latency
Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/38027 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 14 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 644c415..4d1c748 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1026,7 +1026,7 @@ shift_402x = -1;
reg_io_latency |= - (ctrl->timings[channel][slotrank].val_4028 + shift_402x - + (ctrl->timings[channel][slotrank].io_latency + shift_402x - post_timA_min_high) << (4 * slotrank); reg_4024 |= (ctrl->timings[channel][slotrank].val_4024 + @@ -1260,9 +1260,9 @@ printram("4024 -= 2;\n"); continue; } - ctrl->timings[channel][slotrank].val_4028 += 2; + ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { + if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); return MAKE_ERR; @@ -1321,7 +1321,7 @@ else shift_402x = 0;
- ctrl->timings[channel][slotrank].val_4028 += shift_402x; + ctrl->timings[channel][slotrank].io_latency += shift_402x; ctrl->timings[channel][slotrank].val_4024 += shift_402x; printram("4024 += %d;\n", shift_402x); printram("4028 += %d;\n", shift_402x); @@ -1367,7 +1367,7 @@
MCHBAR32(0x3400) = (slotrank << 2) | 0x8001;
- ctrl->timings[channel][slotrank].val_4028 = 4; + ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].val_4024 = 55; program_timings(ctrl, channel);
@@ -1384,7 +1384,7 @@ }
if (all_high) { - ctrl->timings[channel][slotrank].val_4028--; + ctrl->timings[channel][slotrank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -1394,7 +1394,7 @@ } } else if (some_high) { ctrl->timings[channel][slotrank].val_4024++; - ctrl->timings[channel][slotrank].val_4028++; + ctrl->timings[channel][slotrank].io_latency++; printram("4024++;\n"); printram("4028++;\n"); } @@ -1418,14 +1418,14 @@ FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; } - ctrl->timings[channel][slotrank].val_4028 -= mnmx.timA_min_high; + ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; printram("4028 -= %d;\n", mnmx.timA_min_high);
post_timA_change(ctrl, channel, slotrank, &mnmx);
printram("4/8: %d, %d, %x, %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_4024, - ctrl->timings[channel][slotrank].val_4028); + ctrl->timings[channel][slotrank].io_latency);
printram("final results:\n"); FOR_ALL_LANES @@ -1913,7 +1913,7 @@ MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + - ctrl->timings[channel][slotrank].val_4028) << 16); + ctrl->timings[channel][slotrank].io_latency) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; MCHBAR32(0x4218 + 0x400 * channel) = 0;
@@ -2931,12 +2931,12 @@ printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat);
- delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; + delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; printram("normalize %d, %d, %d: delta %d\n", channel, slotrank, lane, delta);
ctrl->timings[channel][slotrank].val_4024 += delta; - ctrl->timings[channel][slotrank].val_4028 += delta; + ctrl->timings[channel][slotrank].io_latency += delta; }
FOR_ALL_POPULATED_CHANNELS { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 6bbc8b3..d11c044 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -54,8 +54,8 @@ struct ram_rank_timings { /* Register 4024. One byte per slotrank. */ u8 val_4024; - /* Register 4028. One nibble per slotrank. */ - u8 val_4028; + /* IO_LATENCY register. One nibble per slotrank. */ + u8 io_latency;
int val_320c;
-
Angel Pons (Code Review) -
Felix Held (Code Review)
-
Kyösti Mälkki (Code Review)