Change in coreboot[master]: skylake: Fixed acpi UPWE disables usb port unexpectedly

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/23848

Change subject: skylake: Fixed acpi UPWE disables usb port unexpectedly
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skylake: Fixed acpi UPWE disables usb port unexpectedly

In PORTSC, Port Enabled/Disabled(PED) is RW1CS.
When there is a USB device attached on system, current UPWE method
will set 1 to PED, this will cause port disabled as it's RW1CS

This change is inspired by xhci_port_state_to_neutral in linux xhci
driver.
It will mask all RO and RWS bits and set WDE and WCE.

Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42
Signed-off-by: Kane Chen 
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/23848/1

diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 08f35bc..f967f65 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -29,14 +29,21 @@
    /* Map ((XMEM << 16) + Local0 in PSCR */
    OperationRegion (PSCR, SystemMemory,
    		 Add (ShiftLeft (Arg2, 16), Local0), 0x10)
-	Field (PSCR, AnyAcc, NoLock, Preserve)
+	Field (PSCR, DWordAcc, NoLock, Preserve)
    {
-		, 25,
-		UPCE, 1,
-		UPDE, 1,
+		PSCT, 32,
    }
-	Store (One, UPCE)
-	Store (One, UPDE)
+
+	Store(PSCT, Local0)
+	/*
+	 * And port status/control reg with RO and RWS bits
+	 * RO bits: 0, 3, 10:13, 30
+	 * RWS bits are 5:8, 9, 14:15, 25:27
+	 */
+	And (Local0, 0x4E00FFE9, Local0)
+	/* Set WCE and WDE bits */
+	Or (Local0, 0x6000000, Local0)
+	Store(Local0, PSCT)
 }

/*