Attention is currently required from: Harsha B R, Haribalaraman Ramasubramanian, Krishna P Bhat D, Ronak Kanabar, Eric Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69396 )
Change subject: mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP ......................................................................
Patch Set 18:
(6 comments)
File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/69396/comment/c0658dd6_1619cb0d PS18, Line 1: # UPDATEME: Current setting is for VP what is VP?
https://review.coreboot.org/c/coreboot/+/69396/comment/fcd9e108_28e338d6 PS18, Line 4: fw_config this is too big file for review, I would recommend to submit a minimal devcietree initially and then incrementally add the feature. At this point, it's dumping everything in one CL.
https://review.coreboot.org/c/coreboot/+/69396/comment/bf265a54_14a9a81f PS18, Line 34: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C port1 can I have access to the schematics to review this code?
https://review.coreboot.org/c/coreboot/+/69396/comment/b6511bb8_42dfed5d PS18, Line 61: register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_3]" = "0" : register "gpio_pm[COMM_4]" = "0" : register "gpio_pm[COMM_5]" = "0" u don't need to set something to zero IMO.
File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/gpio.c:
https://review.coreboot.org/c/coreboot/+/69396/comment/e9fa08c4_dce52d90 PS18, Line 10: /* Pad configuration in ramstage*/ : static const struct pad_config mtlmrvp_gpio_table[] = { : /* TODO: Add GPIO configuration for RVP-M */ : }; keep this separate now, please add MTL-P support alone.
https://review.coreboot.org/c/coreboot/+/69396/comment/6207ef96_abe23e1c PS18, Line 412: case MTLM_LP5_RVP: : printk(BIOS_DEBUG, "configuring MTLM RVP gpios\n"); : gpio_configure_pads(mtlmrvp_gpio_table, ARRAY_SIZE(mtlmrvp_gpio_table)); same