[S] Change in coreboot[master]: soc/amd/mendocino: update FSP parameters for eDP power sequence adjus...

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74789 )

Change subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
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soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment

Add UPD parameter for eDP power sequence adjustment.

The edp_panel_t9_ms parameter is set for bloff to varybloff.

BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table.

Signed-off-by: Chris Wang 
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
2 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/74789/1

diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h
index 5eb7c41..f161038 100644
--- a/src/soc/amd/mendocino/chip.h
+++ b/src/soc/amd/mendocino/chip.h
@@ -179,6 +179,8 @@

/* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */
    uint8_t edp_panel_t8_ms;
+	/* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */
+	uint8_t edp_panel_t9_ms;

};

diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c
index cea26a9..6582a7c 100644
--- a/src/soc/amd/mendocino/fsp_m_params.c
+++ b/src/soc/amd/mendocino/fsp_m_params.c
@@ -171,6 +171,7 @@

mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
    mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
+	mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms;

fsp_fill_pcie_ddi_descriptors(mcfg);
    fsp_assign_ioapic_upds(mcfg);