Patch set updated for coreboot: 06747f2 lynxpoint: expose pch_disable_devfn()

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4250

-gerrit

commit 06747f21a2d8451f8579b70dbf5d04f11a096ca3
Author: Aaron Durbin 
Date:   Wed Jun 19 13:20:37 2013 -0500

lynxpoint: expose pch_disable_devfn()

The function to disable devices was formerly named
    pch_hide_devfn(). This routine was doing more than hiding
    devices. It was disabling them, i.e. turning them off.
    Therefore, rename it to pch_disable_devfn(). Also, allow
    external callers to this function.

Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://gerrit.chromium.org/gerrit/59276
    Reviewed-by: Duncan Laurie 
---
 src/southbridge/intel/lynxpoint/pch.c | 10 +++++-----
 src/southbridge/intel/lynxpoint/pch.h |  1 +
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 05462c5..f13efb0 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -92,7 +92,7 @@ static void pch_enable_d3hot(device_t dev)
 }

/* Set bit in Function Disble register to hide this device */
-static void pch_hide_devfn(device_t dev)
+void pch_disable_devfn(device_t dev)
 {
    switch (dev->path.pci.devfn) {
    case PCI_DEVFN(19, 0): /* Audio DSP */
@@ -432,8 +432,8 @@ static void pch_pcie_enable(device_t dev)
    	/* Do not claim downstream transactions for PCIe ports */
    	new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));

-		/* Hide this device if possible */
-		pch_hide_devfn(dev);
+		/* Disable this device if possible */
+		pch_disable_devfn(dev);
    } else {
    	int fn;

@@ -491,8 +491,8 @@ void pch_enable(device_t dev)
    		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
    	pci_write_config32(dev, PCI_COMMAND, reg32);

-		/* Hide this device if possible */
-		pch_hide_devfn(dev);
+		/* Disable this device if possible */
+		pch_disable_devfn(dev);
    } else {
    	/* Enable SERR */
    	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index c46153c..7c18705 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -162,6 +162,7 @@ void disable_gpe(u32 mask);
 #include <arch/acpi.h>
 #include "chip.h"
 void pch_enable(device_t dev);
+void pch_disable_devfn(device_t dev);
 u32 pch_iobp_read(u32 address);
 void pch_iobp_write(u32 address, u32 data);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);