Change in coreboot[master]: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63367 )

Change subject: soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define
......................................................................

soc/intel: Drop copy-pasted `MSR_VR_MISC_CONFIG2` define

The `MSR_VR_MISC_CONFIG2` was copy-pasted from Haswell/Broadwell code,
but newer processors don't have this MSR.

Change-Id: I1b203aa243ab97e3569f7347b424dd72318bd65f
Signed-off-by: Angel Pons 
---
M src/soc/intel/alderlake/include/soc/msr.h
M src/soc/intel/cannonlake/include/soc/msr.h
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/elkhartlake/include/soc/msr.h
M src/soc/intel/icelake/include/soc/msr.h
M src/soc/intel/jasperlake/include/soc/msr.h
M src/soc/intel/skylake/include/soc/msr.h
M src/soc/intel/tigerlake/include/soc/msr.h
8 files changed, 0 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63367/1

diff --git a/src/soc/intel/alderlake/include/soc/msr.h b/src/soc/intel/alderlake/include/soc/msr.h
index 5bdbf92..f540e81 100644
--- a/src/soc/intel/alderlake/include/soc/msr.h
+++ b/src/soc/intel/alderlake/include/soc/msr.h
@@ -7,6 +7,5 @@

#define MSR_BIOS_DONE		0x151
 #define  ENABLE_IA_UNTRUSTED	(1 << 0)
-#define MSR_VR_MISC_CONFIG2	0x636

#endif
diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h
index cc95fe68..db3a815 100644
--- a/src/soc/intel/cannonlake/include/soc/msr.h
+++ b/src/soc/intel/cannonlake/include/soc/msr.h
@@ -9,7 +9,6 @@
 #define  ENABLE_IA_UNTRUSTED		(1 << 0)
 #define MSR_VR_CURRENT_CONFIG		0x601
 #define MSR_PL3_CONTROL			0x615
-#define MSR_VR_MISC_CONFIG2		0x636
 #define MSR_PLATFORM_POWER_LIMIT	0x65c

#endif
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index 7eb9fdc..70d3a4e 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -67,7 +67,6 @@
 #define MSR_PKG_POWER_SKU_UNIT 0x606
 #define MSR_PKG_POWER_SKU 0x614
 #define MSR_DDR_RAPL_LIMIT 0x618
-#define MSR_VR_MISC_CONFIG2 0x636
 #define MSR_PP0_POWER_LIMIT 0x638
 #define MSR_PP1_POWER_LIMIT 0x640

diff --git a/src/soc/intel/elkhartlake/include/soc/msr.h b/src/soc/intel/elkhartlake/include/soc/msr.h
index 5bdbf92..f540e81 100644
--- a/src/soc/intel/elkhartlake/include/soc/msr.h
+++ b/src/soc/intel/elkhartlake/include/soc/msr.h
@@ -7,6 +7,5 @@

#define MSR_BIOS_DONE		0x151
 #define  ENABLE_IA_UNTRUSTED	(1 << 0)
-#define MSR_VR_MISC_CONFIG2	0x636

#endif
diff --git a/src/soc/intel/icelake/include/soc/msr.h b/src/soc/intel/icelake/include/soc/msr.h
index d716bdb..f6c0ffd 100644
--- a/src/soc/intel/icelake/include/soc/msr.h
+++ b/src/soc/intel/icelake/include/soc/msr.h
@@ -7,6 +7,5 @@

#define MSR_BIOS_DONE			0x151
 #define  ENABLE_IA_UNTRUSTED		(1 << 0)
-#define MSR_VR_MISC_CONFIG2		0x636

#endif
diff --git a/src/soc/intel/jasperlake/include/soc/msr.h b/src/soc/intel/jasperlake/include/soc/msr.h
index 5bdbf92..f540e81 100644
--- a/src/soc/intel/jasperlake/include/soc/msr.h
+++ b/src/soc/intel/jasperlake/include/soc/msr.h
@@ -7,6 +7,5 @@

#define MSR_BIOS_DONE		0x151
 #define  ENABLE_IA_UNTRUSTED	(1 << 0)
-#define MSR_VR_MISC_CONFIG2	0x636

#endif
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index a495799..58b8e411 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -14,7 +14,6 @@
 #define MSR_VR_CURRENT_CONFIG		0x601
 #define MSR_VR_MISC_CONFIG		0x603
 #define MSR_PL3_CONTROL                 0x615
-#define MSR_VR_MISC_CONFIG2		0x636
 #define MSR_PP0_POWER_LIMIT		0x638
 #define MSR_PP1_POWER_LIMIT		0x640
 #define MSR_PLATFORM_POWER_LIMIT        0x65c
diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h
index 5bdbf92..f540e81 100644
--- a/src/soc/intel/tigerlake/include/soc/msr.h
+++ b/src/soc/intel/tigerlake/include/soc/msr.h
@@ -7,6 +7,5 @@

#define MSR_BIOS_DONE		0x151
 #define  ENABLE_IA_UNTRUSTED	(1 << 0)
-#define MSR_VR_MISC_CONFIG2	0x636

#endif