[S] Change in coreboot[main]: spd.h: Move enum ddr5_module_type to ddr5.h

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82123?usp=email )

Change subject: spd.h: Move enum ddr5_module_type to ddr5.h
......................................................................

spd.h: Move enum ddr5_module_type to ddr5.h

Move specific enum ddr5_module_type to <device/dram/ddr5.h>.

Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d
Signed-off-by: Elyes Haouas 
---
M src/device/dram/spd.c
M src/include/device/dram/ddr5.h
M src/include/spd.h
M tests/lib/dimm_info_util-test.c
4 files changed, 18 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/82123/1

diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c
index 4a1e882..c4ccfee 100644
--- a/src/device/dram/spd.c
+++ b/src/device/dram/spd.c
@@ -2,6 +2,7 @@

#include <device/dram/ddr2.h>
 #include <device/dram/ddr3.h>
+#include <device/dram/ddr5.h>
 #include <device/dram/spd.h>
 #include <spd.h>
 #include <stddef.h>
diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h
index ff1604a..37182da 100644
--- a/src/include/device/dram/ddr5.h
+++ b/src/include/device/dram/ddr5.h
@@ -15,6 +15,22 @@
 /** Maximum SPD size supported */
 #define SPD_SIZE_MAX_DDR5	1024

+enum ddr5_module_type {
+	DDR5_SPD_RDIMM = 0x01,
+	DDR5_SPD_UDIMM = 0x02,
+	DDR5_SPD_SODIMM = 0x03,
+	DDR5_SPD_LRDIMM = 0x04,
+	DDR5_SPD_MINI_RDIMM = 0x05,
+	DDR5_SPD_MINI_UDIMM = 0x06,
+	DDR5_SPD_72B_SO_UDIMM = 0x08,
+	DDR5_SPD_72B_SO_RDIMM = 0x09,
+	DDR5_SPD_SOLDERED_DOWN = 0x0b,
+	DDR5_SPD_16B_SO_DIMM = 0x0c,
+	DDR5_SPD_32B_SO_RDIMM = 0x0d,
+	DDR5_SPD_1DPC = 0x0e,
+	DDR5_SPD_2DPC = 0x0f,
+};
+
 /**
  * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
  */
diff --git a/src/include/spd.h b/src/include/spd.h
index 2fe9f96..b456680 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -215,22 +215,6 @@
    DDR4_SPD_32B_SO_RDIMM = 0x0d,
 };

-enum ddr5_module_type {
-	DDR5_SPD_RDIMM = 0x01,
-	DDR5_SPD_UDIMM = 0x02,
-	DDR5_SPD_SODIMM = 0x03,
-	DDR5_SPD_LRDIMM = 0x04,
-	DDR5_SPD_MINI_RDIMM = 0x05,
-	DDR5_SPD_MINI_UDIMM = 0x06,
-	DDR5_SPD_72B_SO_UDIMM = 0x08,
-	DDR5_SPD_72B_SO_RDIMM = 0x09,
-	DDR5_SPD_SOLDERED_DOWN = 0x0b,
-	DDR5_SPD_16B_SO_DIMM = 0x0c,
-	DDR5_SPD_32B_SO_RDIMM = 0x0d,
-	DDR5_SPD_1DPC = 0x0e,
-	DDR5_SPD_2DPC = 0x0f,
-};
-
 enum lpx_module_type {
    LPX_SPD_LPDIMM = 0x07,
    LPX_SPD_NONDIMM = 0x0e,
diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c
index 43fe6c9..3d11416 100644
--- a/tests/lib/dimm_info_util-test.c
+++ b/tests/lib/dimm_info_util-test.c
@@ -2,6 +2,7 @@

#include <device/dram/ddr2.h>
 #include <device/dram/ddr3.h>
+#include <device/dram/ddr5.h>
 #include <dimm_info_util.h>
 #include <spd.h>
 #include <tests/test.h>