Change in coreboot[master]: soc/intel/cannonlake: Fix PEG1 _PRT generation

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Rudolph.
Arthur Heymans has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/58517 )

Change subject: soc/intel/cannonlake: Fix PEG1 _PRT generation
......................................................................

soc/intel/cannonlake: Fix PEG1 _PRT generation

Some weird things happen inside FSP and the routing is not correctly
applied, with PIN D being used but lacking a proper routing in ACPI.
To work around this issue generate _PRT for all 4 INT pins.

Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58517/5