Patch set updated for coreboot: 0195c01 google/panther: Fix thermal zone to use SIO PWM/TACH port 2

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5991

-gerrit

commit 0195c016900a5828d7009c1e2f9fb2cc017cb4d1
Author: Mohammed Habibulla 
Date:   Tue Oct 29 11:02:30 2013 -0700

google/panther: Fix thermal zone to use SIO PWM/TACH port 2

Fan is attached to port 2 instead of 3.
    (panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)

BUG=chrome-os-partner:23563
    TEST=none
    BRANCH=panther

Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
    Signed-off-by: Matt DeVillier 
    Signed-off-by: Paul Menzel 
    Reviewed-on: https://chromium-review.googlesource.com/174984
    Reviewed-by: Duncan Laurie 
    Commit-Queue: Mohammed Habibulla 
    Tested-by: Mohammed Habibulla 
---
 src/mainboard/google/panther/acpi/thermal.asl | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl
index d96d955..d5b1290 100644
--- a/src/mainboard/google/panther/acpi/thermal.asl
+++ b/src/mainboard/google/panther/acpi/thermal.asl
@@ -141,12 +141,12 @@ Scope (_TZ)
    		}
    		Method (_ON)  {
    			Store (0, \FLVL)
-				Store (\F0PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F0PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    		Method (_OFF) {
    			Store (1, \FLVL)
-				Store (\F1PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F1PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    	}
@@ -162,12 +162,12 @@ Scope (_TZ)
    		}
    		Method (_ON)  {
    			Store (1, \FLVL)
-				Store (\F1PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F1PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    		Method (_OFF) {
    			Store (2, \FLVL)
-				Store (\F2PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F2PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    	}
@@ -183,12 +183,12 @@ Scope (_TZ)
    		}
    		Method (_ON)  {
    			Store (2, \FLVL)
-				Store (\F2PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F2PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    		Method (_OFF) {
    			Store (3, \FLVL)
-				Store (\F3PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F3PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    	}
@@ -204,12 +204,12 @@ Scope (_TZ)
    		}
    		Method (_ON)  {
    			Store (3, \FLVL)
-				Store (\F3PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F3PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    		Method (_OFF) {
    			Store (4, \FLVL)
-				Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    	}
@@ -225,12 +225,12 @@ Scope (_TZ)
    		}
    		Method (_ON)  {
    			Store (4, \FLVL)
-				Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    		Method (_OFF) {
    			Store (4, \FLVL)
-				Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Store (\F4PW, _SB.PCI0.LPCB.SIO.ENVC.F2PS)
    			Notify (_TZ.THRM, 0x81)
    		}
    	}