Attention is currently required from: Hung-Te Lin, Raul Rangel, Philipp Hug, Julius Werner, Andrey Petrov, Piotr Król, Jason Glenesk, Michał Żygowski, Marshall Dawson, Christian Walter, Fred Reitberger, ron minnich, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63418 )
Change subject: Replace some ENV_ROMSTAGE with ENV_FIRST_CBMEM_STAGE ......................................................................
Replace some ENV_ROMSTAGE with ENV_FIRST_CBMEM_STAGE
Most of the time we care about the first stage that sets up CBMEM and not explicitly romstage. When linking romstage code in the bootblock it's good to make that assumption flexible so introcude a new symbol 'ENV_FIRST_CBMEM_STAGE'.
Change-Id: I84a126f391b9dd1243c25dedb3d330c99f3fbc19 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/util.c M src/drivers/usb/ehci_debug.c M src/include/cbmem.h M src/include/rules.h M src/lib/cbfs.c M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/lib/program.ld M src/lib/timestamp.c M src/mainboard/bap/ode_e20XX/BiosCallOuts.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/gale/mmu.c M src/mainboard/google/poppy/variants/nautilus/sku.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/storm/mmu.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/pcengines/apu1/BiosCallOuts.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/security/tpm/tspi/log.c M src/soc/amd/common/pi/agesawrapper.c M src/soc/amd/common/pi/def_callouts.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/cavium/cn81xx/sdram.c M src/soc/intel/quark/storage_test.c M src/soc/mediatek/mt8186/emi.c M src/soc/sifive/fu540/clock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/early_init.c M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h 34 files changed, 52 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63418/1
diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 5f52ca0..4015719 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -129,7 +129,7 @@
AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return AGESA_UNSUPPORTED;
return AmdMemoryReadSPD (Func, Data, ConfigPtr); @@ -139,7 +139,7 @@ { AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return AGESA_UNSUPPORTED;
if (info->MemChannelId > 0) diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 31db0b6..1b9c932 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -18,7 +18,7 @@ #include "Dispatcher.h" #endif
-#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE #include <PlatformMemoryConfiguration.h> CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; #endif @@ -262,7 +262,7 @@ if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id) timestamp_add_now(task.ts_entry_id);
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) final = romstage_dispatch(cb, func, StdHeader);
if (ENV_RAMSTAGE) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 9144eaa..5a3b2ec 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -115,7 +115,7 @@ { uint32_t *list_loc;
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) return fsp_hob_list_ptr; list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL; diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 2537b38..7136373 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -77,7 +77,7 @@ return CB_ERR; }
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) soc_validate_fspm_header(hdr);
return CB_SUCCESS; @@ -118,7 +118,7 @@
static inline bool fspm_env(void) { - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) return true; return false; } diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 2fbdf3a..3f8c40d 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -681,7 +681,7 @@ struct ehci_debug_info *dbg_info_cbmem; int rv;
- if (ENV_ROMSTAGE) { + if (ENV_FIRST_CBMEM_STAGE) { /* Move state from CAR to CBMEM. */ struct ehci_debug_info *dbg_info = dbgp_ehci_info(); dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, diff --git a/src/include/cbmem.h b/src/include/cbmem.h index cd7751c..3065420 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -114,7 +114,7 @@ section(".rodata.cbmem_init_hooks"))) = init_fn_; #define POSTCAR_CBMEM_INIT_HOOK(init_fn_) __attribute__((unused)) \ static cbmem_init_hook_t init_fn_ ## _unused_pc_ = init_fn_; -#elif ENV_ROMSTAGE +#elif ENV_FIRST_CBMEM_STAGE #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ section(".rodata.cbmem_init_hooks"))) = init_fn_; @@ -141,14 +141,14 @@
/* Early hooks get executed before other hooks. Use sparingly for hooks that create CBMEM regions which need to remain in a constant location across boot modes. */ -#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE #define ROMSTAGE_CBMEM_INIT_HOOK_EARLY(init_fn_) \ static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ section(".rodata.cbmem_init_hooks_early"))) = init_fn_; #else #define ROMSTAGE_CBMEM_INIT_HOOK_EARLY(init_fn_) __attribute__((unused)) \ static cbmem_init_hook_t init_fn_ ## _unused_rom_ = init_fn_; -#endif /* ENV_ROMSTAGE */ +#endif /* ENV_FIRST_CBMEM_STAGE */
/* * Returns 0 for the stages where we know that cbmem does not come online. diff --git a/src/include/rules.h b/src/include/rules.h index 02b55c5..f7c46b8 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -310,6 +310,8 @@ #define ENV_STAGE_SUPPORTS_COOP 0 #endif
+#define ENV_FIRST_CBMEM_STAGE ENV_ROMSTAGE + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c8ca14c..c330ace 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -106,7 +106,7 @@ static inline bool fspm_env(void) { /* FSP-M is assumed to be loaded in romstage. */ - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) return true; return false; } @@ -134,11 +134,13 @@ if (fspm_env() && CONFIG(FSP_COMPRESS_FSP_M_LZMA)) return true; /* We assume here romstage and postcar are never compressed. */ + if (ENV_FIRST_CBMEM_STAGE && !CONFIG(POSTCAR_STAGE)) + return true; if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) return false; - if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) + if (ENV_FIRST_CBMEM_STAGE && CONFIG(POSTCAR_STAGE)) return false; - if ((ENV_ROMSTAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE)) + if ((ENV_FIRST_CBMEM_STAGE || ENV_POSTCAR) && !CONFIG(COMPRESS_RAMSTAGE)) return false; if (ENV_SMM) return false; diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 4b7c412..f272af1 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -17,7 +17,7 @@
void *cbmem_top(void) { - if (ENV_ROMSTAGE) { + if (ENV_FIRST_CBMEM_STAGE) { static void *top; if (top) return top; @@ -51,7 +51,7 @@ { /* Call one-time hook on expected cbmem init during boot. This sequence assumes first init call is in romstage. */ - if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return;
/* The test is only effective on X86 and when address hits UC memory. */ @@ -106,7 +106,7 @@ * if the imd area was recovered in romstage then S3 resume path * is being taken. */ - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) imd_lockdown(&imd);
/* Add the specified range first */ @@ -206,8 +206,7 @@ imd_region_used(&imd, baseptr, size); }
-#if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) \ - && (ENV_POSTCAR || ENV_ROMSTAGE)) +#if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) && (ENV_POSTCAR || ENV_FIRST_CBMEM_STAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all * get put in the same section even though those strings may never be diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 0e175c6..a7c23ea 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -93,7 +93,7 @@ timestamp_add_now(TS_POSTCAR_END);
/* Call "end of romstage" here if postcar stage doesn't exist */ - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) timestamp_add_now(TS_ROMSTAGE_END);
/* diff --git a/src/lib/program.ld b/src/lib/program.ld index 1c5cda4..04ab6b1 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -24,7 +24,7 @@ *(.text); *(.text.*);
-#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_POSTCAR +#if ENV_RAMSTAGE || ENV_FIRST_CBMEM_STAGE || ENV_POSTCAR . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _cbmem_init_hooks = .; KEEP(*(.rodata.cbmem_init_hooks_early)); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index b92975f..c7497ad 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -215,7 +215,7 @@
/* First time into romstage we make a clean new table. For platforms that travel through this path on resume, ARCH_X86 S3, timestamps are also reset. */ - if (ENV_ROMSTAGE) { + if (ENV_FIRST_CBMEM_STAGE) { ts_cbmem_table = timestamp_alloc_cbmem_table(); } else { /* Find existing table in cbmem. */ @@ -228,7 +228,7 @@ return; }
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) timestamp_sync_cache_to_cbmem(ts_cbmem_table);
/* Seed the timestamp tick frequency in ENV_PAYLOAD_LOADER. */ diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 518bc95..cb985f2 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -180,7 +180,7 @@ AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index;
- if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return AGESA_UNSUPPORTED;
if (CONFIG(BAP_E20_DDR3_1066)) diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index a11b6f9..ed9f75b 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -35,7 +35,7 @@ * Configuring this GPIO as input so that there isn't any ambiguity * in the reading. */ -#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE if (CONFIG(BOARD_GOOGLE_CYAN)) { write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 3b9917c..df0e5c7 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -28,7 +28,7 @@ /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); /* Mark cbmem backing store as ready. */ - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); diff --git a/src/mainboard/google/poppy/variants/nautilus/sku.c b/src/mainboard/google/poppy/variants/nautilus/sku.c index dc1a7ee..527a510 100644 --- a/src/mainboard/google/poppy/variants/nautilus/sku.c +++ b/src/mainboard/google/poppy/variants/nautilus/sku.c @@ -6,7 +6,7 @@
uint32_t variant_board_sku(void) { -#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE uint32_t sku_id = SKU_UNKNOWN; #else static uint32_t sku_id = SKU_UNKNOWN; diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index d76c5e4..d40048d 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -31,7 +31,7 @@ * there is a 10K pullup. Disable the internal pull in romstage so that * there isn't any ambiguity in the reading. */ - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) ssus_disable_internal_pull(WP_STATUS_PAD);
/* WP is enabled when the pin is reading high. */ diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 37b4654..f39cfea 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -25,7 +25,7 @@ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) /* Mark cbmem backing store as ready. */ ipq_cbmem_backing_store_ready(); } else { diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index e80cc12..1bb3238 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -53,7 +53,7 @@ char one_spd_byte;
/* Fake read just to setup SMBUS controller. */ - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) smbus_readSpd(0xa0, &one_spd_byte, 1);
/* Notify the SMC we're alive and kicking, or after a while it will diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 4944a85..e784027 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -38,7 +38,7 @@ { AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return AGESA_UNSUPPORTED;
u8 index = get_spd_offset(); diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index d17dc366..3a977ce 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -107,7 +107,7 @@ { AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return AGESA_UNSUPPORTED;
u8 index = get_spd_offset(); diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 1d6f9ac..266496b 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -39,8 +39,8 @@ if (!cbmem_possibly_online() && !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) return (struct tcpa_table *)_tpm_tcpa_log; - else if (ENV_ROMSTAGE && - !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) { + else if (ENV_FIRST_CBMEM_STAGE + && !CONFIG(VBOOT_RETURN_FROM_VERSTAGE)) { tclt = tcpa_cbmem_init(); if (!tclt) return (struct tcpa_table *)_tpm_tcpa_log; diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index c5e6cac..ff941e1 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -68,7 +68,7 @@ aip->NewStructPtr = buf; aip->NewStructSize = len; } else { - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) aip->AllocationMethod = PreMemHeap; if (ENV_RAMSTAGE) aip->AllocationMethod = PostMemDram; @@ -412,7 +412,7 @@ StdHeader = aip->NewStructPtr; StdHeader->Func = func;
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) status = romstage_dispatch(StdHeader); if (ENV_RAMSTAGE) status = ramstage_dispatch(StdHeader); diff --git a/src/soc/amd/common/pi/def_callouts.c b/src/soc/amd/common/pi/def_callouts.c index 414de6f..a135815 100644 --- a/src/soc/amd/common/pi/def_callouts.c +++ b/src/soc/amd/common/pi/def_callouts.c @@ -23,7 +23,7 @@ #else const BIOS_CALLOUT_STRUCT BiosCallouts[] = { /* Required callouts */ -#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE { AGESA_HALT_THIS_AP, agesa_HaltThisAp }, #endif { AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index ba0f0ee..9ecf58c 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -86,7 +86,7 @@ DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE) + if (!ENV_FIRST_CBMEM_STAGE) return AGESA_UNSUPPORTED;
dev = pcidev_path_on_root(DCT_DEVFN); diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index 080adc0..6d42856 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -29,7 +29,7 @@ #define BDK_RNM_CTL_STATUS 0 #define BDK_RNM_RANDOM 0x100000
-#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE /* Enable RNG for DRAM init */ static void rnm_init(void) { diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 04c6736..f20e62b 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -159,7 +159,7 @@
/* Get the structure addresses */ media = NULL; - if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) media = (struct storage_media *)drivers_storage; else media = cbmem_find(CBMEM_ID_STORAGE_DATA); @@ -225,7 +225,7 @@ } #endif
-#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE static void copy_storage_structures(int is_recovery) { struct storage_media *media; diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c index 6e25441..38722b32 100644 --- a/src/soc/mediatek/mt8186/emi.c +++ b/src/soc/mediatek/mt8186/emi.c @@ -15,7 +15,7 @@ const struct mem_chip_info *mc; size_t size = 0;
- if (ENV_ROMSTAGE) { + if (ENV_FIRST_CBMEM_STAGE) { size = mtk_dram_size(); printk(BIOS_INFO, "dram size (romstage): %#lx\n", size); return size; diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 977f938..fedf3e2 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -56,7 +56,7 @@ #define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
/* Clock initialization should only be done in romstage. */ -#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE struct pll_settings { unsigned int divr:6; unsigned int divf:9; @@ -247,7 +247,7 @@
asm volatile ("fence"); } -#endif /* ENV_ROMSTAGE */ +#endif /* ENV_FIRST_CBMEM_STAGE */
/* Get the core clock's frequency, in KHz */ int clock_get_coreclk_khz(void) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6ed3dce..dfc326f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -310,6 +310,6 @@
setup_pch_gpios(&mainboard_gpio_map);
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) enable_smbus(); } diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 4647bf1..a99e534 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -57,7 +57,7 @@
#define TCO_BASE 0x60
-#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE void i82801gx_early_init(void) { enable_smbus(); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index f781098..b459407 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -47,7 +47,7 @@ { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) enable_smbus();
/* Set up RCBA. */ diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 327c8fc..82a0f30 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -69,7 +69,7 @@ { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
- if (ENV_ROMSTAGE) + if (ENV_FIRST_CBMEM_STAGE) enable_smbus();
printk(BIOS_DEBUG, "Setting up static southbridge registers..."); diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h index b1a346a..cbbcd30 100644 --- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -2,7 +2,7 @@ #define AGESA_ENTRY_CFG_H
-#if ENV_ROMSTAGE +#if ENV_FIRST_CBMEM_STAGE
#define AGESA_ENTRY_INIT_RESET TRUE #define AGESA_ENTRY_INIT_EARLY TRUE
-
Arthur Heymans (Code Review)