[S] Change in coreboot[main]: mb/google/brox: Set up FW_CONFIG

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79854?usp=email )

Change subject: mb/google/brox: Set up FW_CONFIG
......................................................................

mb/google/brox: Set up FW_CONFIG

Brox project has FW_CONFIG bits already set up in the project file for
the retimer and for storage, so making sure that the brox device tree
matches those settings.  Also, moving the storage devices to brox
overridetree.cb as they are specific to this board.

BUG=b:311450057,b:300690448
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
     will check if this helps detect the storage device in the factory

Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
M src/mainboard/google/brox/variants/brox/overridetree.cb
2 files changed, 31 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79854/1

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index 23db754..c1c561b 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -173,21 +173,6 @@
    	end
    	device ref heci1 on end
    	device ref sata on end
-		device ref pcie4_0 on
-			# Enable CPU PCIE RP 1 using CLK 3
-			register "cpu_pcie_rp[CPU_RP(1)]" = "{
-				.clk_req = 3,
-				.clk_src = 3,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref ish on
-			chip drivers/intel/ish
-				register "add_acpi_dma_property" = "true"
-				device generic 0 on end
-			end
-		end
-		device ref ufs on end
    	device ref uart0 on end
    	device ref gspi1 on end
    	device ref pch_espi on
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index c9767bc..c0d5c2c 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -1,3 +1,15 @@
+fw_config
+	field RETIMER 0 1
+		option RETIMER_UNKNOWN			0
+		option RETIMER_BYPASS			1
+		option RETIMER_JHL8040			2
+	end
+	field STORAGE 2
+		option STORAGE_UFS			0
+		option STORAGE_NVME			1
+	end
+end
+
 chip soc/intel/alderlake
    device domain 0 on
    	device ref igpu on
@@ -147,5 +159,24 @@
    			device generic 0 on end
    		end
    	end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 3
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 3,
+				.clk_src = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			probe STORAGE STORAGE_NVME
+		end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+			probe STORAGE STORAGE_UFS
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+		end
    end
 end