[M] Change in coreboot[master]: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params

[Michał Żygowski (Code Review)]

Attention is currently required from: Kacper Stojek, Lean Sheng Tan, Werner Zeh.

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72404 )

Change subject: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
......................................................................

Patch Set 2:

(1 comment)

File src/soc/intel/elkhartlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/72404/comment/30a4cdda_6673bf4d 
PS2, Line 159: if (CONFIG_TTYS0_BASE == 0x3f8)
             : 			m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
             : 		else if (CONFIG_TTYS0_BASE == 0x2f8)
             : 			m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_2F8;
> Yes I know, but since the other 2 configs are exposed they should be handled as well. […]

So how do you suggest to handle them?