Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30814
Change subject: soc/intel/baytrail: Use non-evict CAR setup ......................................................................
soc/intel/baytrail: Use non-evict CAR setup
The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this.
Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/Kconfig A src/cpu/intel/car/non-evict/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/romstage/Makefile.inc D src/soc/intel/baytrail/romstage/cache_as_ram.inc 6 files changed, 21 insertions(+), 218 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30814/1
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index f5d0ab9..18f73b4 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -36,3 +36,4 @@ source src/cpu/intel/turbo/Kconfig source src/cpu/intel/common/Kconfig source src/cpu/intel/microcode/Kconfig +source src/cpu/intel/car/non-evict/Kconfig diff --git a/src/cpu/intel/car/non-evict/Kconfig b/src/cpu/intel/car/non-evict/Kconfig new file mode 100644 index 0000000..faf13e7 --- /dev/null +++ b/src/cpu/intel/car/non-evict/Kconfig @@ -0,0 +1,5 @@ +config CPU_HAS_L2_ENABLE_MSR + bool + help + Select this in Kconfig of CPU sockets/SOC where the CPU + has an MSR to enable the L2 CPU cache diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d2beaa7..3203159 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -24,6 +24,7 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e
.global bootblock_pre_c_entry
@@ -133,6 +134,18 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr
+#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR) + /* + * Enable the L2 cache. Currently this assumes that this + * only affect socketed CPU's for which this is always valid, + * hence the static preprocesser. + */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr +#endif + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index ade908f..e824ee4 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -40,6 +40,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select CPU_INTEL_COMMON + select CPU_HAS_L2_ENABLE_MSR
config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index aa10ba6..f1a3463 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += romstage.c romstage-y += raminit.c diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc deleted file mode 100644 index 4326636..0000000 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cpu/x86/msr.h> - -#include "fmap_config.h" - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $IA32_MCG_CAP, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %eax, %eax - xorl %edx, %edx -1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Clear/disable fixed MTRRs */ - mov $fixed_mtrr_list_size, %ebx - xor %eax, %eax - xor %edx, %edx - -clear_fixed_mtrr: - add $-2, %ebx - movzwl fixed_mtrr_list(%ebx), %ecx - wrmsr - jnz clear_fixed_mtrr - - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ - movl $0x80000008, %eax - cpuid - movb %al, %cl - sub $32, %cl - movl $1, %edx - shl %cl, %edx - subl $1, %edx - - /* Preload high word of address mask (in %edx) for Variable - * MTRRs 0 and 1. - */ -addrsize_set_high: - xorl %eax, %eax - movl $MTRR_PHYS_MASK(0), %ecx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - wrmsr - - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - rdmsr - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRR_PHYS_BASE(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - mov $_car_stack_end, %esp - - /* Need to align stack to 16 bytes at call instruction. Account for - the pushes below. */ - andl $0xfffffff0, %esp - subl $4, %esp - - /* push TSC and BIST to stack */ - movd %mm0, %eax - pushl %eax /* BIST */ - movd %mm2, %eax - pushl %eax /* tsc[63:32] */ - movd %mm1, %eax - pushl %eax /* tsc[31:0] */ - -before_c_entry: - post_code(0x2a) - call bootblock_c_entry_bist - - /* Should never see this postcode */ - post_code(POST_DEAD_CODE) - -.Lhlt: - hlt - jmp .Lhlt - -fixed_mtrr_list: - .word MTRR_FIX_64K_00000 - .word MTRR_FIX_16K_80000 - .word MTRR_FIX_16K_A0000 - .word MTRR_FIX_4K_C0000 - .word MTRR_FIX_4K_C8000 - .word MTRR_FIX_4K_D0000 - .word MTRR_FIX_4K_D8000 - .word MTRR_FIX_4K_E0000 - .word MTRR_FIX_4K_E8000 - .word MTRR_FIX_4K_F0000 - .word MTRR_FIX_4K_F8000 -fixed_mtrr_list_size = . - fixed_mtrr_list
Kyösti Mälkki has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/30814 )
Change subject: soc/intel/baytrail: Use non-evict CAR setup ......................................................................
soc/intel/baytrail: Use non-evict CAR setup
The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this.
Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/romstage/Makefile.inc D src/soc/intel/baytrail/romstage/cache_as_ram.inc 3 files changed, 2 insertions(+), 218 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30814/6
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30814 )
Change subject: soc/intel/baytrail: Use non-evict CAR setup ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30814 )
Change subject: soc/intel/baytrail: Use non-evict CAR setup ......................................................................
soc/intel/baytrail: Use non-evict CAR setup
The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this.
Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/30814 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/romstage/Makefile.inc D src/soc/intel/baytrail/romstage/cache_as_ram.inc 3 files changed, 2 insertions(+), 218 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index ade908f..e824ee4 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -40,6 +40,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select CPU_INTEL_COMMON + select CPU_HAS_L2_ENABLE_MSR
config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index aa10ba6..f1a3463 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += romstage.c romstage-y += raminit.c diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc deleted file mode 100644 index 3dcf019..0000000 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cpu/x86/msr.h> - -#include "fmap_config.h" - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $IA32_MCG_CAP, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %eax, %eax - xorl %edx, %edx -1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Clear/disable fixed MTRRs */ - mov $fixed_mtrr_list_size, %ebx - xor %eax, %eax - xor %edx, %edx - -clear_fixed_mtrr: - add $-2, %ebx - movzwl fixed_mtrr_list(%ebx), %ecx - wrmsr - jnz clear_fixed_mtrr - - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ - movl $0x80000008, %eax - cpuid - movb %al, %cl - sub $32, %cl - movl $1, %edx - shl %cl, %edx - subl $1, %edx - - /* Preload high word of address mask (in %edx) for Variable - * MTRRs 0 and 1. - */ -addrsize_set_high: - xorl %eax, %eax - movl $MTRR_PHYS_MASK(0), %ecx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - wrmsr - - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - rdmsr - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRR_PHYS_BASE(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - mov $_car_stack_end, %esp - - /* Need to align stack to 16 bytes at call instruction. Account for - the pushes below. */ - andl $0xfffffff0, %esp - subl $4, %esp - - /* push TSC and BIST to stack */ - movd %mm0, %eax - pushl %eax /* BIST */ - movd %mm2, %eax - pushl %eax /* tsc[63:32] */ - movd %mm1, %eax - pushl %eax /* tsc[31:0] */ - -before_c_entry: - post_code(0x2a) - call bootblock_c_entry_bist - - /* Should never see this postcode */ - post_code(POST_DEAD_CODE) - -.Lhlt: - hlt - jmp .Lhlt - -fixed_mtrr_list: - .word MTRR_FIX_64K_00000 - .word MTRR_FIX_16K_80000 - .word MTRR_FIX_16K_A0000 - .word MTRR_FIX_4K_C0000 - .word MTRR_FIX_4K_C8000 - .word MTRR_FIX_4K_D0000 - .word MTRR_FIX_4K_D8000 - .word MTRR_FIX_4K_E0000 - .word MTRR_FIX_4K_E8000 - .word MTRR_FIX_4K_F0000 - .word MTRR_FIX_4K_F8000 -fixed_mtrr_list_size = . - fixed_mtrr_list
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)