Change in coreboot[master]: soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Nick Vaccaro, Alex Levin, Patrick Rudolph.
Hello build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Nick Vaccaro, Alex Levin, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/61849

to look at the new patch set (#3).

Change subject: soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
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soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq

As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.

This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.

Software must initiate the next SPI transaction when this bit is 0.

Add non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.

BUG=b:215255210
TEST=Able to boot brya and verified SPI read/write is successful.

Signed-off-by: Subrata Banik 
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
---
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61849/3