Attention is currently required from: Sean Rhodes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 )
Change subject: src/mainboard: Add Star Labs labtop series ......................................................................
Patch Set 9: Code-Review+1
(7 comments)
Patchset:
PS9: Few more nits, mostly LGTM
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/55128/comment/75c7b640_a8a12305 PS6, Line 11: ### Purism : : [Purism](https://www.puri.sm) sells laptops with a focus on user privacy and : security; part of that effort is to minimize the amount of proprietary and/or : binary code. Their laptops ship with a blob-free OS and coreboot firmware : with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
I was bundling all the documentation into one, seemed to miss the relevant 'Documentation/mainboard/ […]
Ack
File Documentation/mainboard/starlabs/labtop.md:
https://review.coreboot.org/c/coreboot/+/55128/comment/5036d716_739f5921 PS9, Line 120: higher than **1.5.6** will work. : ![fwupd version](https://cdn.shopify.com/s/files/1/2059/5897/files/fwupdV.png?v=1611136423) : On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: : sounds like you mean 1.5.6 and greater will work?
File src/mainboard/starlabs/labtop/Kconfig:
https://review.coreboot.org/c/coreboot/+/55128/comment/834a527b_5709426f PS6, Line 26: # select HAVE_IFD_BIN : # select HAVE_ME_BIN
ME and Descriptor aren't in the blobs repository, which causes the build to fail. […]
Ack
File src/mainboard/starlabs/labtop/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/55128/comment/31540f01_8ace18fe PS9, Line 55: Sorry I mean there's a tab between #define and EC_GPE_SWI, should be a space
File src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex:
PS6:
No, just as the hex files already existed in the tree. […]
This is fine; the spd_tools are really neat, though, if you have access to the datasheet for the memory part; it can generate an SPD file for some Intel & AMD chipsets automatically. I think it would need some porting work for CML or KBL, though.
File src/mainboard/starlabs/labtop/variants/cml/romstage.c:
https://review.coreboot.org/c/coreboot/+/55128/comment/96dc6be9_e799eb78 PS6, Line 41: (gpio_get(GPP_H6) < 2) | (gpio_get(GPP_E23) < 1) | gpio_get(GPP_E22);
suggestion: use `gpio_base2_value` function, e.g.: […]
Done