Change in coreboot[master]: [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25020

Change subject: [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1
......................................................................

[UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1

LPB1 in NVS is never set by coreboot. Drop this copy-pasta and see if
it's less confusing for the OS.

Change-Id: Ic265afc2b27c261ebdde42337c9dcc7c1ccc84f3
Signed-off-by: Nico Huber 
---
M src/soc/intel/braswell/acpi/device_nvs.asl
M src/soc/intel/braswell/acpi/lpe.asl
M src/soc/intel/braswell/include/soc/device_nvs.h
M src/soc/intel/braswell/lpe.c
4 files changed, 3 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/25020/1

diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl
index 0d4bc3c..d67e71f 100644
--- a/src/soc/intel/braswell/acpi/device_nvs.asl
+++ b/src/soc/intel/braswell/acpi/device_nvs.asl
@@ -75,7 +75,7 @@
 C0B1,	32,	/* MMC BAR1 */
 C1B1,	32,	/* SDIO BAR1 */
 C2B1,	32,	/* SD Card BAR1 */
-LPB1,	32,	/* LPE BAR1 */
+RSV1,	32,	/* reserved */

/* Extra */

diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl
index 145e608..c1369b0 100644
--- a/src/soc/intel/braswell/acpi/lpe.asl
+++ b/src/soc/intel/braswell/acpi/lpe.asl
@@ -20,12 +20,10 @@
    Name (_CID, "808622A8")
    Name (_UID, 1)
    Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8")
-	Name (_PR0, Package () { PLPE })

Name (RBUF, ResourceTemplate()
    {
    	Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)
-		Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)
    	Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2)
    	Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
    	{
@@ -59,10 +57,6 @@
    	CreateDwordField (^RBUF, ^BAR0._BAS, BAS0)
    	Store (\LPB0, BAS0)

-		/* Update BAR1 from NVS */
-		CreateDwordField (^RBUF, ^BAR1._BAS, BAS1)
-		Store (\LPB1, BAS1)
-
    	/* Update LPE FW from NVS */
    	CreateDwordField (^RBUF, ^BAR2._BAS, BAS2)
    	Store (\LPFW, BAS2)
@@ -84,31 +78,4 @@
    		Return (0x0)
    	}
    }
-
-	OperationRegion (KEYS, SystemMemory, LPB1, 0x100)
-	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
-	{
-		Offset (0x84),
-		PSAT, 32,
-	}
-
-	PowerResource (PLPE, 0, 0)
-	{
-		Method (_STA)
-		{
-			Return (1)
-		}
-
-		Method (_OFF)
-		{
-			Or (PSAT, 0x00000003, PSAT)
-			Or (PSAT, 0x00000000, PSAT)
-		}
-
-		Method (_ON)
-		{
-			And (PSAT, 0xfffffffc, PSAT)
-			Or (PSAT, 0x00000000, PSAT)
-		}
-	}
 }
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 268655e..a97ac54 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -56,7 +56,7 @@
    /* BAR 0 */
    u32	lpss_bar1[14];
    u32	scc_bar1[3];
-	u32	lpe_bar1;
+	u32	reserved1;

/* Extra */
    u32	lpe_fw; /* LPE Firmware */
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 8ec944b..b65c158 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -75,10 +75,8 @@
    	return;
    }

-	/* Save BAR0, BAR1, and firmware base  to ACPI NVS */
+	/* Save BAR0 and firmware base  to ACPI NVS */
    assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
-	/* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */
-	/* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);  */
    assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);

/* Device is enabled in ACPI mode */