Change in coreboot[master]: soc/intel/alderlake: Add support for power cycle and SLP signal duration - coreboot-gerrit

24 Sep 2021


      Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57891 )
Change subject: soc/intel/alderlake: Add support for power cycle and SLP signal duration
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Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/57891/comment/f927ba72_c30e4a90 
PS2, Line 470: 	 *  2 = 4s
...
yes, this is FSP order not register order. […]
Thank you. Why can’t we use enums or macros instead of the numbers?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0
Gerrit-Change-Number: 57891
Gerrit-PatchSet: 2
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