Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
[TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
With a pentium 4 CPU running WP XIP is not possible. To speed up execution copying romstage to CAR might work?
TEST: does it boot? is it faster?
Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/memlayout.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/socket_mPGA604/Kconfig 3 files changed, 20 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/1
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 9fd9889..ed89894 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -39,7 +39,7 @@ #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) + ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_DCACHE_ROMSTAGE_SIZE)
#include EARLY_MEMLAYOUT #elif ENV_VERSTAGE diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 2cd0c5e..fdb5ddc 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,9 +23,17 @@ .set ap_sipi_vector_in_rom, 0xff #endif
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_ROMSTAGE_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#if (CACHE_AS_RAM_BASE & (CACHE_AS_RAM_SIZE - 1)) +#error "CONFIG_DCACHE_RAM_BASE is not aligned!" +#endif + +#if ((CACHE_AS_RAM_SIZE & (CACHE_AS_RAM_SIZE - 1)) != 0) +#error "Cache-as-Ram size must be a power of 2!" +#endif + #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4ec46e0..5f9eb9c 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -15,6 +15,7 @@ select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select NO_XIP_EARLY_STAGES
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -25,7 +26,7 @@
config DCACHE_RAM_BASE hex - default 0xfefc0000 + default 0xfef0000
config DCACHE_RAM_SIZE hex @@ -35,4 +36,12 @@ hex default 0x2000
+config DCACHE_ROMSTAGE_SIZE + hex + default 0xc000 + +config ROMSTAGE_ADRR + hex + default 0xfef4000 + endif # CPU_INTEL_SOCKET_MPGA604
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 1:
Does not reach romstage, dies in cbfs_load_and_decompress(), rdev_readat() for case CBFS_COMPRESS_NONE. But I am not convinced rdev is properly setup yet.
Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
[TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
With a pentium 4 CPU running WP XIP is not possible. To speed up execution copying romstage to CAR might work?
TEST: does it boot? is it faster?
Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/memlayout.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/socket_mPGA604/Kconfig 3 files changed, 20 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
#2 boots and romstage is much faster.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
(1 comment)
Patch Set 2:
#2 boots and romstage is much faster.
Nice! I wonder how it will compare on targets with XIP.
https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... File src/cpu/intel/socket_mPGA604/Kconfig:
https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... PS2, Line 29: 0xffef0000 any reason why?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
before:
0:1st timestamp 367 13:starting to load romstage 1,004,157 (1,003,790) 14:finished loading romstage 1,007,503 (3,346) 1:start of rom stage 1,035,148 (27,644) 2:before ram initialization 1,118,794 (83,645) 3:after ram initialization 1,901,509 (782,714) 4:end of romstage 2,626,474 (724,965)
after:
0:1st timestamp 367 13:starting to load romstage 1,058,627 (1,058,259) 14:finished loading romstage 1,077,024 (18,396) 1:start of rom stage 1,104,382 (27,358) 2:before ram initialization 1,104,392 (9) 3:after ram initialization 1,355,040 (250,648) 4:end of romstage 1,367,352 (12,311)
Times with CBMEM console only, about 500ms of romstage improvement is in printk().
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... File src/cpu/intel/socket_mPGA604/Kconfig:
https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... PS2, Line 29: 0xffef0000
any reason why?
You suggested value below 1 << 28, bottom 64 MiB? We want to stay above TOLM but need to avoid some of FWH RW bank registers that extend below ROM size.
I was supposed to put 0xfef00000 here.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... File src/cpu/intel/socket_mPGA604/Kconfig:
https://review.coreboot.org/c/coreboot/+/36564/2/src/cpu/intel/socket_mPGA60... PS2, Line 29: 0xffef0000
You suggested value below 1 << 28, bottom 64 MiB? We want to stay above TOLM but need to avoid some of FWH RW bank registers that extend below ROM size.
I was supposed to put 0xfef00000 here.
Looks like I made a typo and indeed meant 0xfef00000 too.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
27 entries total:
0:1st timestamp 367 11:start of bootblock 894,120 (893,753) 12:end of bootblock 956,393 (62,272) 13:starting to load romstage 1,062,414 (106,020) 14:finished loading romstage 1,080,891 (18,476) 1:start of rom stage 1,110,899 (30,007)
Huh.. it takes 895 ms to reach 11:start of bootblock, and there is only assembly before that. Maybe instruction fetch from FWH is just slow or i82801dx configuration lacks some boost. Note that this is a dual-socket board that does the AP SIPI wakeup thing.
That microcode update in cache_as_ram.S only took 5 ms.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
Patch Set 2:
27 entries total:
0:1st timestamp 367 11:start of bootblock 894,120 (893,753) 12:end of bootblock 956,393 (62,272) 13:starting to load romstage 1,062,414 (106,020) 14:finished loading romstage 1,080,891 (18,476) 1:start of rom stage 1,110,899 (30,007)
Huh.. it takes 895 ms to reach 11:start of bootblock, and there is only assembly before that. Maybe instruction fetch from FWH is just slow or i82801dx configuration lacks some boost. Note that this is a dual-socket board that does the AP SIPI wakeup thing.
That microcode update in cache_as_ram.S only took 5 ms.
The AP SIPI wakeup is there for HT siblings? Do your CPU have those? If not it, might be possible to skip it (e.g. use the core2 code and comment out the XIP caching).
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
Another option is to put an rdtsc during the CAR and replace the initial timestamps in %mmx to debug it.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
27 entries total:
0:1st timestamp 367 11:start of bootblock 894,120 (893,753) 12:end of bootblock 956,393 (62,272) 13:starting to load romstage 1,062,414 (106,020) 14:finished loading romstage 1,080,891 (18,476) 1:start of rom stage 1,110,899 (30,007)
Huh.. it takes 895 ms to reach 11:start of bootblock, and there is only assembly before that. Maybe instruction fetch from FWH is just slow or i82801dx configuration lacks some boost. Note that this is a dual-socket board that does the AP SIPI wakeup thing.
That microcode update in cache_as_ram.S only took 5 ms.
The AP SIPI wakeup is there for HT siblings? Do your CPU have those? If not it, might be possible to skip it (e.g. use the core2 code and comment out the XIP caching).
Yes, HT siblings. This is the platform the SIPI stuff was originally developed on.
Kyösti Mälkki has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
[TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
With a pentium 4 CPU running WP XIP is not possible. To speed up execution copying romstage to CAR might work?
TEST: does it boot? is it faster?
Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/memlayout.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/socket_mPGA604/Kconfig 3 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 3:
Patchset #3, with CB:36595 fix in place for HT-enabled cpu.
0:1st timestamp 367 11:start of bootblock 26,421 (26,054) 12:end of bootblock 88,533 (62,112) 13:starting to load romstage 194,554 (106,020)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36564 )
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Patch Set 3:
Patch Set 3:
Patchset #3, with CB:36595 fix in place for HT-enabled cpu.
0:1st timestamp 367 11:start of bootblock 26,421 (26,054) 12:end of bootblock 88,533 (62,112) 13:starting to load romstage 194,554 (106,020)
I think one might even further speed up thing by compressing the romstage as it seems boot device is still one of the biggest bottleneck.
Hello Kyösti Mälkki, Patrick Rudolph, Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36564
to look at the new patch set (#4).
Change subject: [TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
[TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR
With a pentium 4 CPU running WP XIP is not possible. To speed up execution copying romstage to CAR might work?
TEST: does it boot? is it faster? Does compressing ROMSTAGE speed up things?
Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/memlayout.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/socket_mPGA604/Kconfig 3 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/4
Hello Kyösti Mälkki, Patrick Rudolph, Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36564
to look at the new patch set (#5).
Change subject: [WIP]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
[WIP]cpu/intel/socket_mPGA604: Run romstage from CAR
With a pentium 4 CPU running WP XIP is not possible. To speed up execution copy romstage to CAR.
With a default build stack + other symbols take up 0x2e50 bytes, so increase the CAR region, which must be a power of 2 and set ROMSTAGE_ADDR at a comfortable distance.
TEST: Does compressing ROMSTAGE, speed up things even more?
Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/socket_mPGA604/Kconfig 1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/5
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36564?usp=email )
Change subject: [WIP]cpu/intel/socket_mPGA604: Run romstage from CAR ......................................................................
Abandoned
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
-
Stefan Reinauer (Code Review)