Arthur Heymans has uploaded this change for review.

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[TESTONLY]cpu/intel/socket_mPGA604: Run romstage from CAR

With a pentium 4 CPU running WP XIP is not possible. To speed up
execution copying romstage to CAR might work?

TEST: does it boot? is it faster?

Change-Id: I4c35d09b87b545944a4465ff695953d1e8a811e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/arch/x86/memlayout.ld
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/socket_mPGA604/Kconfig
3 files changed, 20 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36564/1

diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 9fd9889..ed89894 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -39,7 +39,7 @@
 #elif ENV_ROMSTAGE
 	/* The 1M size is not allocated. It's just for basic size checking.
 	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
-	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
+	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_DCACHE_ROMSTAGE_SIZE)
 
 	#include EARLY_MEMLAYOUT
 #elif ENV_VERSTAGE
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 2cd0c5e..fdb5ddc 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,9 +23,17 @@
 .set ap_sipi_vector_in_rom, 0xff
 #endif
 
-#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_ROMSTAGE_SIZE)
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
+#if (CACHE_AS_RAM_BASE & (CACHE_AS_RAM_SIZE - 1))
+#error "CONFIG_DCACHE_RAM_BASE is not aligned!"
+#endif
+
+#if ((CACHE_AS_RAM_SIZE & (CACHE_AS_RAM_SIZE - 1)) != 0)
+#error "Cache-as-Ram size must be a power of 2!"
+#endif
+
 #if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
 #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 4ec46e0..5f9eb9c 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -15,6 +15,7 @@
 	select C_ENVIRONMENT_BOOTBLOCK
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
+	select NO_XIP_EARLY_STAGES
 
 # mPGA604 are usually Intel Netburst CPUs which should have SSE2
 # but the ramtest.c code on the Dell S1850 seems to choke on
@@ -25,7 +26,7 @@
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xfefc0000
+	default 0xfef0000
 
 config DCACHE_RAM_SIZE
 	hex
@@ -35,4 +36,12 @@
 	hex
 	default 0x2000
 
+config DCACHE_ROMSTAGE_SIZE
+	hex
+	default 0xc000
+
+config ROMSTAGE_ADRR
+	hex
+	default 0xfef4000
+
 endif # CPU_INTEL_SOCKET_MPGA604

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