Change in coreboot[master]: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Jingle Hsu, Subrata Banik, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58576 )

Change subject: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table
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Patch Set 1:

(1 comment)

File src/soc/intel/common/smbios.c:

https://review.coreboot.org/c/coreboot/+/58576/comment/f807fcc7_6fed6e3f 
PS1, Line 84: 			dimm->bus_width |= 0x10;
> That's what it appeared to me when I was referring the SPD spec for DDR5 and LP5 […]

Shouldn't we use `smbios_bus_width_to_spd_width` here and update that instead?