[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR

[Angel Pons (Code Review)]

Attention is currently required from: Felix Held, [e-mail].

Angel Pons has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email )

Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
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Patch Set 5:

(2 comments)

File src/soc/intel/common/block/include/intelblocks/itss.h:

https://review.coreboot.org/c/coreboot/+/85012/comment/b998765b_37c36cdc?usp... :
PS5, Line 27: #define PCR_ITSS_PIR	0x3140
            : #define PCI_ITSS_PIR(i)	(PCR_ITSS_PIR + (i) * 2)
nit: alignment?

```suggestion
#define PCR_ITSS_PIR		0x3140
#define PCI_ITSS_PIR(i)		(PCR_ITSS_PIR + (i) * 2)
```

File src/soc/intel/common/block/itss/itss.c:

https://review.coreboot.org/c/coreboot/+/85012/comment/daea10bc_416e4fd1?usp... :
PS5, Line 138: enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin)
Where is this function used?