Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11436
-gerrit
commit 871576e927e2fa5b60bc0208ba74a5c0ae5da813 Author: robbie zhang robbie.zhang@intel.com Date: Tue Aug 25 16:13:53 2015 -0700
intel/kunimitsu: port the change from glados for correctly reading lid switch and SPI write protect for fill_lb_gpios() to coreboot table.
BUG=chrome-os-partner:43707 BRANCH=none TEST=build and boot on kunimits Signed-off-by: robbie zhang robbie.zhang@intel.com
Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b Signed-off-by: Patrick Georgi patrick@georgi-clan.de Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680 Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5 Original-Reviewed-on: https://chromium-review.googlesource.com/295580 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Wenkai Du wenkai.du@intel.com Original-Tested-by: Wenkai Du wenkai.du@intel.com --- src/mainboard/intel/kunimitsu/chromeos.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 66be521..d2cfeb7 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -57,13 +58,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void) { - /* Default to force open */ - return 1; + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); }
-/* The dev-switch is virtual */ int get_developer_mode_switch(void) { + /* No physical developer mode switch. */ return 0; }
@@ -87,5 +88,6 @@ int clear_recovery_mode_switch(void)
int get_write_protect_state(void) { - return 0; + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); }